
Preliminary W742E81A/W742C81A
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6.11 WatchDog Timer (WDT) and WatchDog Timer Register(WDTR)
The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from
unknown errors. When the corresponding option code bit of the WDT set to 1, the WDT is enabled,
and if the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is
F
OSC
/2048. The input clock of the WDT can be switched to F
OSC
/16384 (or F
OSC
/2048) by setting
WDTR.3 to 1. The contents of the WDT can be reset by the instruction CLR WDT. In normal
operation, the application program must reset WDT before it overflows. A WDT overflow indicates
that operation is not under control and the chip will be reset. The WDT overflow period is 1 S when
the sub-system clock (Fs) is 32 KHz and WDT clock input is Fs/2048. When the corresponding option
code bit of the WDT set to 0, the WDT function is disabled. The organization of the Divider0 and
watchdog timer is shown in Figure 6-5.
Q1
Q2
Q9
Q10 Q11 Q12
Q14
Q13
Fosc
S
R
Q
HEF.0
IEF.0
1. Reset
2. CLR EVF,#01H
3. CLR DIVR0
EVF.0
Hold mode release
(HCF.0)
Divider interrupt (INT0)
. . .
Overflow signal
WDT
Enable
Disable
WDTR.3
Fosc/2048
Fosc/16384
Option code is "0"
Qw1
R
Qw2
R
Qw4
R
Qw3
R
Divider0
System Reset
1. Reset
2. CLR WDT
Option code is "1"
WDTR.2
Q1
Q2
Q9
Q10 Q11 Q12
Q14
Q13
S
R
Q
HEF.4
IEF.4
1.
2. CLR EVF,#10H
3. CLR DIVR1
EVF.4
Hold mode release
(HCF.4)
Divider interrupt
(INT1)
. . .
Divider1
Fss/2048
Fss/16384
Fss=Fs or Fosc/128
SCR.3
Figure 6-5 Organization of Divider0, Divider1 and WatchDog Timer