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參數(shù)資料
型號(hào)： W742C81A
廠商： WINBOND ELECTRONICS CORP
元件分類： 微控制器/微處理器
英文描述： 4-BIT MICROCONTROLLER
中文描述： 4-BIT, FLASH, MICROCONTROLLER, UUC100
封裝： DIE-100
文件頁(yè)數(shù)： 16/45頁(yè)
文件大小： 567K
代理商： W742C81A
Preliminary W742E81A/W742C81A
- 16 -
6.12 Timer/Counter
6.12.1 Timer 0 (TM0)
Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into
TM0 by executing the MOV TM0L(TM0H),R instructions. When the MOV TM0L(TM0H),R instructions
are executed, it will stop the TM0 down-counting (if the TM0 is down-counting) and reset the MR0.3 to
0, and the specified value can be loaded into TM0. Then we can set MR0.3 to 1, that will cause the
event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decreases and underflow to FFH,
Timer 0 stops operating and generates an underflow (EVF.1 = 1). Then, if the Timer 0 interrupt
enable flag has been set (IEF.1 = 1), the interrupt is executed, while if the hold release enable flag 1
has been set (HEF.1 = 1), the hold state is terminated. The Timer 0 clock input can be set as
F
OSC
/1024 or F
OSC
/4 by setting MR0.0 to 1 or resetting MR0.0 to 0. The default timer value is
F
OSC
/4. The organization of Timer 0 is shown in Figure 6-6.
If the Timer 0 clock input is F
OSC
/4:
Desired Timer 0 interval = (preset value +1)
×
4
×
1/F
OSC
If the Timer 0 clock input is F
OSC
/1024:
Desired Timer 0 interval = (preset value +1)
×
1024
×
1/F
OSC
Preset value: Decimal number of Timer 0 preset value
F
OSC
: Clock oscillation frequency
Fosc/4
Fosc/1024
Enable
Disable
1. Reset
2. CLR EVF,#02H
3. Reset MR0.3 to 0
4.MOV TM0L,R or MOV TM0H,R
8-Bit Binary
Down Counter
(Timer 0)
S
R
Q
HEF.1
IEF.1
Hold mode release (HCF.1)
Timer 0 interrupt (INT1)
1. Reset
2. CLR EVF,#02H
3.Set MR0.3 to 1
EVF.1
MR0.0
Set MR0.3 to 1
4
4
MOV TM0H,R
MOV TM0L,R
Figure 6-6 Organization of Timer 0
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