
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 103 -
Revision A3.0
14. PULSE-WIDTH-MODULATED (PWM) OUTPUTS
14.1 PWM Features
The PWM block supports the following features;
z
Four 12-bit PWM channels or complementary pairs:
4 independent PWM outputs: PWM0, PWM2, PWM4 & PWM6.
4 complementary PWM pairs with insertion of programmable dead-time:
(PWM0,PWM1), (PWM2,PWM3), (PWM4,PWM5), (PWM6,PWM7)
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Three operation mode:
Edge aligned mode, Center aligned mode and Single shot mode.
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Programmable dead-time insertion between paired PWMs.
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Output override control for Electrically Commutated Motor operation.
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Hardware/software brake protection.
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Support 2 independent interrupts:
Interrupt request when up/down counter comparison matched or underflow.
Interrupt request when external brake asserted.
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Flexible operation in debug mode.
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High Source/Sink current.
The outputs for PWM0 to PWM7 are on P2[5:0] (PWM[5:0]) and P5[1:0] (PWM [7:6]) respectively.
After CPU reset, the internal output of each PWM channel depends on the output controls and polarity
settings. The interval between successive outputs is controlled by a 12–bit up/down counter which
uses the oscillator frequency with configurable internal clock prescaler as its input. The PWM counter
clock, has the frequency as the clock source F
PWM
= F
OSC
/Prescaler. The following is the block
diagram for PWM.
Figure 14-1: PWM Block Diagram