
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 185 -
Revision A3.0
P40AH, P40AL:
The Base address registers for comparator of P4.0. P40AH contains the high-order byte of address;
P40AL contains the low-order byte of address.
P41AH, P41AL:
The Base address registers for comparator of P4.1. P41AH contains the high-order byte of address;
P41AL contains the low-order byte of address.
P42AH, P42AL:
The Base address registers for comparator of P4.2. P42AH contains the high-order byte of address;
P42AL contains the low-order byte of address.
P43AH, P43AL:
The Base address registers for comparator of P4.3. P43AH contains the high-order byte of address;
P43AL contains the low-order byte of address.
PORT 4
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
P4.3
P4.2
P4.1
P4.0
Mnemonic: P4
P4.3-0
Address: A5h
Port 4 is a bi-directional I/O port with internal pull-ups.
PORT 4 CHIP-SELECT POLARITY
Bit:
7
6
5
4
3
2
1
0
P43INV
P42INV
P42INV
P40INV
-
PWDNH
RMWFP
PUP0
Mnemonic: P4CSIN
P4xINV
Address: A2h
The active polarity of P4.x when it is set as a chip-select strobe output. High =
Active High. Low = Active Low.
Set PWDNH to logic 1 then ALE and PSEN will keep high state, clear this bit to logic
0 then ALE and PSEN will output low during power down mode.
Control Read Path of Instruction “Read-Modify-Write”. When this bit is set, the read
path of executing “read-modify-write” instruction is from port pin otherwise from
SFR.
Enable Port 0 weak pull up.
PWDNH
RMWFP
PUP0