
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 57 -
Revision A3.0
All the bits in this SFR have unrestricted read access. The bits of POR, WDIF, EWT and RWT require
Timed Access (TA) procedure to write. The remaining bits have unrestricted write accesses. Please
refer TA register description.
PWMP COUNTER LOW BITS REGISTER
Bit:
7
6
5
4
3
2
1
0
PWMP.7
PWMP.6
PWMP.5
PWMP.4
PWMP.3
PWMP.2
PWMP.1
PWMP.0
Mnemonic: PWMPL
Address: D9h
BIT
NAME
FUNCTION
7~0 PWMP.7 ~PWMP.0
PWM Counter Low Bits Register.
PWM0 LOW BITS REGISTER
Bit:
7
6
5
4
3
2
1
0
PWM0.7
PWM0.6
PWM0.5
PWM0.4
PWM0.3
PWM0.2
PWM0.1
PWM0.0
Mnemonic: PWM0L
Address: DAh
BIT
NAME
FUNCTION
7~0 PWM0.7 ~PWM0.0
PWM 0 Low Bits Register.
NVM LOW BYTE ADDRESS
Bit:
7
6
5
4
3
2
1
0
NVMADDR
L.7
NVMADDR
L.6
NVMADDR
L.5
NVMADDR
L.4
NVMADDR
L.3
NVMADDR
L.2
NVMADDR
L.1
NVMADDR
L.0
Mnemonic: NVMADDRL
Address: DBh
BIT
NAME
FUNCTION
7~0 NVMADDRL.7~ NVMADDRL.0 The NVM low byte address.
PWM CONTROL REGISTER 1
Bit:
7
6
5
4
3
2
1
0
PWMRUN
Load
PWMF
CLRPWM
PWM6I
PWM4I
PWM2I
PWM0I
Mnemonic: PWMCON1
Address: DCh
BIT
NAME
FUNCTION
7
PWMRUN
0 = The PWM is not running.
1 = The PWM counter is running.
6
Load
This bit is auto cleared by hardware after the PWMP and PWMn are transferred
to counter and compare register:
0 = The registers value of PWMP and PWMn is never loaded to counter and
compare registers.
1 = The PWMP and PWMn registers load value to counter and compare
registers at the counter underflow/match.