
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 37 -
Revision A3.0
CAPTURE CONTROL 1 REGISTER
Bit:
7
6
5
4
3
2
1
0
-
-
ENF2
ENF1
ENF0
CPTF2
CPTF1/
CPTF0
Mnemonic: CAPCON1
Address: A4h
BIT
NAME
FUNCTION
7-6
-
Reserved.
5
ENF2
Enable filter for capture input 2.
4
ENF1
Enable filter for capture input 1.
3
ENF0
Enable filter for capture input 0.
2
CPTF2
Input capture/reload 2 interrupt flag.
1
CPTF1/DIRF
Input Capture 2 flag share the same bit with DIRF flag.
IC mode
- Input capture/reload 1 interrupt flag.
QEI mode
- Direction changed interrupt flag. Bit is set by hardware when
direction index (DIR) changes state and direction change interrupt is
requested if it is enabled. DIRF is cleared by software.
0
CPTF0/QEIF
Input Capture
0
flag share the same bit with QEI flag.
IC mode
– Input capture/reload 0 interrupt flag.
QEI mode
- QEI interrupt flag.
1. In free-counting mode, if Pulse Counter overflows or underflows.
2. In compare-counting mode, if Pulse Counter overflows from Maximum
Count to zero or underflows from zero to Maximum Count.
PORT 4
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
P4.3
P4.2
P4.1
P4.0
Mnemonic: P4
Address: A5h
BIT
NAME
FUNCTION
7-4
-
Reserved.
3-2
P4
GPIO.
1
P4
GPIO. Alternate function T2EX/IC2 for Timer 2 external trigger/Input Capture 2
respectively.
0
P4
GPIO. Alternate function STADC. External start ADC trigger input.