
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 8 -
Revision A3.0
5. PIN DESCRIPTION
SYMBOL
TYPE
INITIAL
STATE
DESCRIPTIONS
EA
I
-
EXTERNAL ACCESS ENABLE:
This pin forces the processor to
execute from external ROM. The ROM address and data are not
presented on the bus if the
EA
pin is high.
Note: This pin has no internal pull-up or pull-down. The pin
needs externally pull-up to execute from internal APROM. For
executing from external APROM, the pin needs externally pull-
down. The pin state is internally latched during all reset. User
needs to take note that changes to /EA pin state after reset will
not be effective.
PSEN
O H
High
PROGRAM STORE ENABLE:
PSEN
enables the external ROM
data in the Port 0 address/data bus. When internal ROM access is
performed,
PSEN
strobe signal will not be output from this pin.
ADDRESS LATCH ENABLE:
ALE enables the address latch that
separates the address from the data on Port 0.
RESET:
Set this pin high for two machine cycles while the
oscillator is running to reset the device.
CRYSTAL 1:
Crystal oscillator input or external clock input.
CRYSTAL 2:
Crystal oscillator output.
GROUND
: Ground potential.
POWER SUPPLY:
Supply voltage for operation.
LCD voltage input. Positive (+) supply voltage terminal for LCD
biasing.
Analog power supply.
Analog ground potential.
PWM power supply.
PWM ground potential.
PORT 0
: Port 0 is an open-drain bi-directional I/O port. This port
also provides a multiplexed low byte address/data bus during
accesses to external memory. There is an embedded weakly pull-
up resistor on each port 0 pin which can be enabled or disabled by
setting or clearing of PUP0, bit0 in A2h. The ports have alternate
functions which are described below:
P0.0, MISO
P0.1, MOSI
P0.2, SPCLK
P0.3, /SS
P0.4, INT2
P0.5, INT3
P0.6, INT4
P0.7, INT5
ALE
O H
High
RST
I L
-
XTAL1
XTAL2
V
SS
V
DD
VLCD1,
VLCD2
AVDD
AVSS
VDDPWM I
VSSPWM
I
O
I
I
-
-
-
-
I
-
I
I
-
-
-
-
I
P0.0
P0.7
I/O
D S H
High-Z