
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 21 -
Revision A3.0
Continued
SYMBOL
DEFINITION
ADD
RESS
C2H
C1H
MSB
LSB
ENLD
SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0 xxxx xxxxB
(BF)
SM0_1/F
E_1
PWM4.1
1
PWM7E
N
N
N
N
N
BIT_ADDRESS,
SYMBOL
RESET
T3MOD
SBUF1
TIMER 3 MODE CONTROL
SERIAL BUFFER 1
ICEN2
ICEN1
ICEN0
T3CR
-
-
-
0000 0xxxB
SCON1
SERIAL CONTROL 1
C0H
(BE)
SM1_1
(BD)
SM2_1
(BC)
REN_1
(BB)
TB8_1
(BA)
RB8_1
(B9)
TI_1
(B8)
RI_1
0000 0000B
PWM4H
PWM 4 HIGH BITS
REGISTER
PWM OUTPUT ENABLE
REGISTER
PWM PIN OUTPUT SOURCE
SELECT
PWM OUTPUT STATE
REGISTERS
PWM OUTPUT OVERRIDE
CONTROL REGISTERS
BFH
-
-
-
-
PWM4.1
0
PWM2E
N
PWM4.9 PWM4.8 xxxx 0000B
PWMEN
BEH
PWM6E
PWM5E
PWM4E
PWM3E
PWM1E
N
PWM0E
N
0000 0000B
PIO
BDH PIO7
PIO6
PIO5
PIO4
PIO3
PIO2
PIO1
PIO0
0000 0000B
POVD
BCH POVD.7 POVD.6 POVD.5 POVD.4 POVD.3 POVD.2 POVD.1 POVD.0 0000 0000B
POVM
BBH POVM.7 POVM.6 POVM.5 POVM.4 POVM.3 POVM.2 POVM.1 POVM.0 0000 0000B
SADEN1
SLAVE ADDRESS MASK 1
BAH
SADEN1
.7
SADEN.
7
(BF)
-
SADEN1
.6
SADEN.
6
(BE)
PADC
PADCH
SADEN1
.5
SADEN.
5
(BD)
PT2
PT2H
SADEN1
.4
SADEN.
4
(BC)
PS
PSH
SADEN1
.3
SADEN.
3
(BB)
PT1
PT1H
SADEN1
.2
SADEN.
2
(BA)
PX1
PX1H
SADEN1
.1
SADEN.
1
(B9)
PT0
PT0H
SADEN1
.0
SADEN.
0
(B8)
PX0
PX0H
0000 0000B
SADEN
SLAVE ADDRESS MASK
B9H
0000 0000B
IP
INTERRUPT PRIORITY
B8H
0000 0000B
IPH
INTERRUPT HIGH PRIORITY B7H
EXTENDED INTERRUPT
HIGH PRIORITY 1
RELOAD CAPTURE 3 HIGH
REGISTER
RELOAD CAPTURE 3 LOW
REGISTER
PORT 7
PORT 6
PORT 5
x000 0000B
EIP1H
B6H
-
-
PNVMIH PCPTFH PT3H
PBKFH
PPWMH PSPIH
xx00 0000B
RCAP3H
B5H
RCAP3H
.7
RCAP3L
.7
SEG.31
SEG.23
SEG.15
RCAP3H
.6
RCAP3L
.6
SEG.30
SEG.22
SEG.14
RCAP3H
.5
RCAP3L
.5
SEG.29
SEG.21
SEG.13
RCAP3H
.4
RCAP3L
.4
SEG.28
SEG.20
SEG.12
(B4)
T0/
ICO/QE
A
NCE
D4
A12
A4
RCAP3H
.3
RCAP3L
.3
SEG.27
SEG.19
SEG.11
RCAP3H
.2
RCAP3L
.2
SEG.26
SEG.18
SEG.10
RCAP3H
.1
RCAP3L
.1
SEG.25 SEG.24 1111 1111B
SEG.17 SEG.16 1111 1111B
PWM7
PWM6
RCAP3H
.0
RCAP3L
.0
0000 0000B
RCAP3L
B4H
0000 0000B
P7
P6
P5
B3H
B2H
B1H
1111 1111B
P3
PORT 3
B0H
(B7)
RD
(B6)
WR
(B5)
T1/
IC1/QEB
(B3)
/INT1
(B2)
/INT0
(B1)
TXD
(B0)
RXD
1111 1111B
SFRCN
SFRFD
SFRAH
SFRAL
F/W FLASH CONTROL
F/W FLASH DATA
F/W FLASH HIGH ADDRESS ADH A15
F/W FLASH LOW ADDRESS ACH A7
AFH
AEH D7
-
WFWIN
D6
A14
A6
NOE
D5
A13
A5
CTRL3
D3
A11
A3
LCDPT.
3
SADDR1
.3
SADDR.
3
(AB)
ET1
CCH2.3
/MAXCN
TH.3
CTRL2
D2
A10
A2
LCDPT.
2
SADDR1
.2
SADDR.
2
(AA)
EX1
CCH2.2
/MAXCN
TH.2
CTRL1
D1
A9
A1
LCDPT.
1
SADDR1
.1
SADDR.
1
(A9)
ET0
CCH2.1
/MAXCN
TH.1
CCL2.1
/MAXCN
TL.1
T2EX/IC
2
CTRL0
D0
A8
A0
LCDPT.
0
SADDR1
.0
SADDR.
0
(A8)
EX0
CCH2.0
/MAXCN
TH.0
CCL2.0
/MAXCN
TL.0
x011 1111B
xxxx xxxxB
0000 0000B
0000 0000B
LCDPT
LCD POINTER
ABH -
-
-
-
xxxx 0000B
SADDR1
SLAVE ADDRESS 1
AAH
SADDR1
.7
SADDR.
7
(AF)
EA
CCH2.7
/MAXCN
TH.7
CCL2.7
/MAXCN
TL.7
SADDR1
.6
SADDR.
6
(AE)
EADC
CCH2.6
MAXCN
TH.6
CCL2.6
/MAXCN
TL.6
SADDR1
.5
SADDR.
5
(AD)
ET2
CCH2.5
/MAXCN
TH.5
CCL2.5
/MAXCN
TL.5
SADDR1
.4
SADDR.
4
(AC)
ES
CCH2.4
/MAXCN
TH.4
CCL2.4
/MAXCN
TL.4
0000 0000B
SADDR
SLAVE ADDRESS
A9H
0000 0000B
IE
INTERRUPT ENABLE
A8H
0000 0000B
CCH2/MAX
CNTH
INPUT CAPTURE 2 HIGH
REGISTER/ MAXIMUM
COUNTER HIGH REGISTER
A7h
0000 0000B
CCL2/MAX
CNTL
INPUT CAPTURE 2 LOW
REGISTER/ MAXIMUM
COUNTER LOW REGISTER
A6h
CCL2.3
/MAXCN
TL.3
CCL2.2
/MAXCN
TL.2
0000 0000B
P4
PORT 4
A5H
-
-
-
-
P4.3
P4.2
STADC xxxx 1111B