
Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 90 -
Revision A3.0
11.2 Priority Level Structure
There are four priority levels for the interrupts; highest, high, low and lowest. The other interrupt
source can be individually set to either high or low levels. Naturally, a higher priority interrupt cannot
be interrupted by a lower priority interrupt. However there exists a predefined hierarchy amongst the
interrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve
simultaneous requests having the same priority level. This hierarchy is defined as shown below; the
interrupts are numbered starting from the highest priority to the lowest.
SOURCE
FLAG
VECTOR
ADDRESS
FLAG CLEARED BY
PRIORITY
LEVEL
External Interrupt 0
IE0
0003H
Hardware, Follow the
inverse of pin
1(highest)
Timer 0 Overflow
TF0
000BH
Hardware, software
2
External Interrupt 1
IE1
0013H
Hardware, Follow the
inverse of pin
3
Timer 1 Overflow
TF1
001BH
Hardware, software
4
Serial Port
RI + TI
0023H
Software
5
Timer 2 Overflow
TF2 + EXF2
002BH
Software
6
A/D Converter
ADCI
0033H
Software
7
I2C Channel
I2C1 SI
003BH
Software
8
Serial Port 1
RI_1 + TI_1
007BH
Software
9
SPI interrupt
SPIF + MODF +
SPIOVF
0083H
Software
10
External Interrupt 2
IE2
0043H
Hardware, software
11
External Interrupt 3
IE3
004BH
Hardware, software
12
External Interrupt 4
IE4
0053H
Hardware, software
13
External Interrupt 5
IE5
005BH
Hardware, software
14
PWM Period
PWMF
0073H
Software
15
PWM Brake
BKF
006BH
Software
16
Timer 3 Overflow
TF3
008BH
Software
17
Capture
Input/Direction
Interrupt/QEI
CPTF0/QEIF+
CPTF1/DIRF+
CPTF2
0093H
Software
18
NVM Interrupt
NVMF
009BH
Software
19
Watchdog Timer
WDIF
0063H
Software
20
Table 11- 1: Priority structure of interrupts