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參數資料
| 型號： | W9330F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Code Division Spread Spectrum Cordless Telephone Controller(具有編碼分劃和擴展頻普技術的無繩電話控制器) |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 11/26頁 |
| 文件大小： | 170K |
| 代理商： | W9330F |
Preliminary W9330F
Publication Release Date: August 1998
- 11 -
Revision A1
CER is asserted when the parity error is detected in any subframe. It is cleared when the status
register is read by the system controller.
4. Clock Generator
The W9330F operates with the system crystal or oscillator at 19.2 MHz.
The CLK_IN signal is the system clock input pin. All internal timing signals, including the chip rate and
sampling rate, are generated from this main clock. The system clock can be supplied by an external
source or can be generated through the on-chip oscillator circuit.
The on-chip oscillator circuit consists of four pins, OSC_IN, OSC_OUT, OSC_EN and CLK_OUT.
The OSC_IN and OSC_OUT pins are connected to an external crystal. OSC_EN should be asserted
(low) to enable the oscillator circuit. CLK_OUT is the buffered output of the oscillator which is capable
of driving multiple external devices. If the on-chip oscillator is to be used to generate the system clock
input, CLK_OUT and CLK_IN should be connected together externally. If the system clock is provided
by external source other than the on-chip oscillator, the oscillator circuit can be turned off by de-
asserting OSC_EN. The external clock source should drive the CLK_IN input directly. In power down
mode the OSC_EN signal can be de-asserted to stop the oscillator and the system clock to conserve
power.
The W9330F contains a programmable clock generator to generate a divided-down CPU clock to the
system controller. The CPU clock output from the W9330F can be programmed to run at 9.6 MHz,
4.8 MHz, 2.4 MHz (CLK_IN divided by 2, 4 or 8) or off. After system reset, the CPU clock runs at 2.4
MHz (divided by 8).
5. Codec Interface
The W9330F supports all ADPCM Codec chips that are compatible with the CCITT G.721
recommendation and ANSI T1.301. Once the communication is established between the master and
slave, the W9330F interfaces directly with the codec to retrieve transmit data and send out received
data. It generates codec framing signal COD_SYNC and clocking signal COD_CLK.
The COD_SYNC signal is a 8 KHz signal generated from the system clock. The COD_CLK signal is
600 KHz, equivalent to 75X of COD_SYNC.
The rising edge of COD_SYNC defines a data frame for the codec chip. The COD_SYNC signal
remains high for four COD_CLK cycles. The codec chip samples four bits of data at the falling edge
of COD_CLK while COD_SYNC is high. User data recovered by the de-spreader of the W9330F is
stored in on-chip FIFO and then outputted on DR to be sampled by the codec, synchronized with
COD_SYNC and COD_CLK signals.
Data to be transmitted by the W9330F is generated by the codec at the first four rising edge of
COD_CLK of each data frame. The transmit data, DT, is sampled by the W9330F at the falling edge
of COD_CLK and stored in on-chip FIFO. During transmission time, data is read from the FIFO and
sent out to the RF module through the spreader.
The following timing diagram illustrates the timing of the codec interface.
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