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參數(shù)資料
| 型號(hào)： | W9330F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 無(wú)繩電話/電話 |
| 英文描述： | Code Division Spread Spectrum Cordless Telephone Controller(具有編碼分劃和擴(kuò)展頻普技術(shù)的無(wú)繩電話控制器) |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 13/26頁(yè) |
| 文件大小： | 170K |
| 代理商： | W9330F |
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Preliminary W9330F
Publication Release Date: August 1998
- 13 -
Revision A1
7. Reset
The W9330F can be reset through hardware or software. Hardware reset is when the RESET input is
asserted with the system clock running. Software reset is done by writing "one" to the RST bit in the
command register. Hardware reset and software reset are very similar except that some control
registers return to their default values through hardware reset while some other control registers
return to the default value through either reset. The register description section of this data sheet
describes the conditions when each register returns to default value. It should be noted that some
register values such as IO expansion ports are not affected by either reset. After system power-up,
the RESET signal must be asserted for at least ten clock cycles before the system can function
properly.
When the RESET signal is de-asserted, the W9330F enters the standby mode. During standby, all
the control registers hold its current value and the system controller interface and I/O expansion
blocks are fully functional. All control registers, including the command registers, should be
programmed by the controller during standby mode. Once programming is completed, the STRT bit in
the command register can be set to start operation.
8. Advanced Power Management
The W9330F has three power down modes: sleep, freeze and standby.
Sleep mode has the lowest level of power consumption. The device enters sleep mode when
OSC_EN is de-asserted. If the system clock, CLK_IN, is supplied by an external source, it should
also stop toggling. Most of the function of the W9330F, including CPU_CLK, general purpose timer,
CODEC interface, are stopped in sleep mode. The controller interface and I/O ports are still
operational. All control registers and IO ports retain their values and control register can still be
accessed through the controller interface. However, read the status register would not clear the IRQ
signal. In order to conserve power, controller bus activity and register access should be keep to the
minimum.
To exit from sleep mode, the device must go through the standby mode. The device must first be
reset through hardware reset or software reset. While reset is on, OSC_EN or external clock can be
re-asserted. The hardware or software reset can then be removed and the device is now in standby
mode.
Freeze mode is the second lowest level of power saving. The device enters freeze mode when the
CHIP_EN input is de-asserted. It is similar to sleep mode except that since the system clock is still
toggling, the CPU_CLK and general purpose timer functions are still operational. Exit from freeze
mode is similar to exit from sleep mode.
Standby mode is entered by executing a hardware or software reset while system clock is running. In
standby mode, the device is operational except that communication protocol is not running. When the
STRT bit in the command register is set, the device enters active mode and becomes fully
operational. The device receives and transmits data only in active mode.
In order to ensure that the device enters sleep or freeze mode with all output pins at the proper
setting, the device must be first reset through hardware or software before entering either sleep or
freeze modes.
If the on-chip oscillator is not used and the system clock is supplied by an external source, the
OSC_EN pin must be de-asserted at all time to avoid any device switching noise and to minimize
power consumption.
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