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參數資料
| 型號： | W9330F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Code Division Spread Spectrum Cordless Telephone Controller(具有編碼分劃和擴展頻普技術的無繩電話控制器) |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 15/26頁 |
| 文件大小： | 170K |
| 代理商： | W9330F |
Preliminary W9330F
Publication Release Date: August 1998
- 15 -
Revision A1
10. Data Encryption
Data transmission using code division spread spectrum technology is inherently secure due to the use
of PN code. The W9330F adds another level of data security by allowing the user to encrypt the
transmit data on a frame-by-frame basis. The transmit data can be encoded by a random sequence
generated on-chip. Only receivers programmed with the same random sequence can decipher the
transmit frame.
The random sequence is generated by the following polynomial
f(X)
:
f(X) = 1 + X
2
+ X
3
+ X
5
+ X
11
Unique random sequence is defined by the user by initializing the value of X
0
to X
7
through one of the
control registers.
11. Error Detection
Error detection is built-in to the W9330F. Every 8 bits of the transmit data is accompanied by a parity
bit. Parity generation and detection is automatically performed. The CER bit in the status register and
CER output pin signals when parity error is detected. They are set within each subframe when parity
is detected and are cleared when the status register is read.
12. Signal Strength Indicator
Code division spread spectrum (CD/SS) devices receive data by matching the received signal with
the expected PN code. The signal strength indicator indicates how well the received signal correlates
with the expected PN code. The indicator is the accumulative value of the correlation factor of each
received data starting from the beginning of each frame. If the subframe interrupt bit, SUBE, is turned
on and the signal strength indicator is read on each subframe and frame end interrupt, the value is
always increasing from the first interrupt until the last interrupt of the receive frame. This value
provides a very good indication of how clean the communication link is as seen by the W9330F.
The signal strength indicator is a relative value. Higher value indicates stronger PN code correlation.
Value of 5F(Hex) can be expected at frame end when strong signal is received. When frame error is
detected on the receive frame, the signal strength indicator does not carry any meaningful value.
13. I/O Expansion Ports
The W9330F contains four I/O expansion ports to facilitate system design. Port A and port B are
output ports with PA7: 0 and PB7: 0 as the corresponding output pins. Port A can be tri-stated by de-
asserting the OEA input pin. Port B is divided into two halves, the lower half, PB3: 0, has regular
output buffers and is always enabled. The upper half, PB7: 4, has open drain outputs. Both port A and
port B are bit address-able as well as byte address-able.
Port C is an input port with pins PC7:0. It can be read through the control register and also feeds to a
combinational output signal. The output signal, WAKEUP, is defined with the following logical
function:
WAKEUP = PC0 | PC1 | PC2 | PC3 | ~PC4 | ~PC5| ~PC6 | ~PC7
Port D is a general purpose I/O port. It functions as an output port when the IO control bit in register
44(Hex) is cleared. If the IO control bit is set, the output buffers on pins PD7: 0 are tri-stated and the
input value can be read.
The internal registers holding the value of all ports are static registers and are not affected by
software reset or power management functions. All ports can be written or read even when the
system clock is turned off. Upon hardware reset, port D becomes an input port and the registers
holding the output values are set. Port B is also set by hardware reset.
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