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參數資料
| 型號： | W9330F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Code Division Spread Spectrum Cordless Telephone Controller(具有編碼分劃和擴展頻普技術的無繩電話控制器) |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 17/26頁 |
| 文件大小： | 170K |
| 代理商： | W9330F |
Preliminary W9330F
Publication Release Date: August 1998
- 17 -
Revision A1
Address 00: Command 1 / Status
Both the Command 1 register and Status register are mapped to register address 00. When this
address is written, the input data is written into Command 1 register in the following format.
0
0
REC
0
ANTSW
RST
STRT
STKY
Bit 7, 6 and 4 must be written as zero.
Bit 5: Receive only bit. If this bit is set and the device operates in slave mode, it does not transmit
any response frame even when a valid acquisition burst frame is detected.
Bit 3: Antenna switch bit. The output signal ANTSW reflects the value of ANTSW bit. When the value
of ANTSW bit changes, the output signal ANTSW will change state only when the PLL_SW output
change state.
Bit 2: Soft reset bit. Setting this bit would have similar effect as asserting the RESET external input
pin(hardware reset). The RST bit is cleared when the external RESET pin is asserted. Write one to
this bit to enter soft reset state and write zero to exit soft reset.
Bit 1: Start bit. The device starts normal operation when this bit is set.
Bit 0: STICKY bit. this bit enables the sticky count register (1FH) when it is set. See description of the
sticky count register for more detail.
Reset value:
bit 7 to 3 are cleared by hardware reset and not affected by software reset.
bit 2 is cleared by hardware reset.
bit 1 to 0 are cleared by both hardware and software reset.
When register location 00 is read, the status register value outputted with the following format.
LK
RLK
ANTSW
SUBF
FER
CER
TND
RND
This register should read by the system controller at each interrupt. Bit 4 to 0 and the interrupt request
pin, IRQ , are cleared after each read.
Bit 7: Lock bit. This bit is set whenever an acquisition frame has been received by the device. Once
set, this bit remains set unless the communication link is broken.
Bit 6: Rlock bit. This bit is set whenever an empty frame has been received by the device. Once set,
this bit remains set unless the communication link is broken.
Bit 5: Has the same value as the ANTSW output pin.
Bit 4: Sub-frame end. This bit is set whenever an interrupt is generated at the end of a subframe.
When interrupt is generated at the end of a complete data frame, this bit is cleared. The bit have
valid information only when FER bit is cleared.
Bit 3: Frame Error. This bit is set when the device fail to detect the frame preamble or when system
ID mis-match. When this bit is set, bit 4, 2, 1 and 0 does not hold valid information.
Bit 2: This bit is set if parity error is detected in any subframe. This bit is cleared every time this
register is read.
Bit 1: Transmit End. This bit is set at the end of a transmit frame or subframe.
Bit 0: Received End. This bit is set at the end of a received frame or subframe.
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