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參數資料
| 型號： | W9330F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Code Division Spread Spectrum Cordless Telephone Controller(具有編碼分劃和擴展頻普技術的無繩電話控制器) |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 5/26頁 |
| 文件大小： | 170K |
| 代理商： | W9330F |
Preliminary W9330F
Publication Release Date: August 1998
- 5 -
Revision A1
Table 3: RF Module Interface
PARAMETER
PIN
TYPE
DESCRIPTIONS
ANTSW
48
OUT
Antenna Switch. This signal can be used to switch between two
available antenna in the system. The ANTSW signal changes
state only at the beginning of the gap time between frames.
PLL_SW
60
OUT
Phase Lock Loop Switch. This signal switches the transceiver
phase lock loop between transmit and receive mode. PLL_SW is
high during transmission and the preceding gap time. It is low
when receiving.
RF_PWR
59
OUT
RF Power. This signal switches the transmitter on and off during
full duplex operation. It is high when transmitting and low when
receiving. It is enveloped by TX_ENV to ensure the proper
timing sequence when the RF module switches direction.
RX_DATA
54
IN
Received Data. PN data recovered from the RF module. Input to
the de-spreader circuitry.
TX_DATA
56
OUT
Transmit Data. Output of the spreader circuitry to be transmitted
by the RF module. TX_DATA is a high drive output but is not 5V
tolerant. All other external pins are 5V tolerant.
TX_ENV
58
OUT
Transmitter Power. Switches the direction of the RF module. It is
high when transmitting and low when receiving. It envelopes
RF_PWR by 5.5 chip time in both edges.
Table 4: System Interface
PARAMETER
PIN
TYPE
DESCRIPTIONS
BSYNC_IN
63
IN_D
Burst Synchronization Input. This signal is designed to use in a
PBX setup where multiple master is located together. All the
BSYNC_IN signals should be connected together so that all
masters start transmission at the same time.
BSYNC_OUT
64
OUT
Burst Synchronization Output. This signal is designed to use in a
PBX setup where multiple master is located together. The
BSYNC_OUT of one master should be used as synchronization
source and connected to the BSYNC_IN to all masters, including
its own BSYNC_IN to synchronize transmission. If only one
master issused, the BSYNC_OUT should be connected to the
BSYNC_IN of the same device.
CHIP_EN
81
IN
Chip Enable. This signal controls the internal clocks of the
device. When it is de-asserted, the internal clocks remain
unchanged (time freeze). The CPU_CLK signal and internal
timer are still operational while CHIP_EN is de-asserted. The
device is in operation mode only when CHIP_EN is asserted.
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