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參數(shù)資料
| 型號： | W9330F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Code Division Spread Spectrum Cordless Telephone Controller(具有編碼分劃和擴展頻普技術(shù)的無繩電話控制器) |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 21/26頁 |
| 文件大小： | 170K |
| 代理商： | W9330F |
Preliminary W9330F
Publication Release Date: August 1998
- 21 -
Revision A1
Address 2C - 2F: PN code, write only, no default value
CODETHREE[7:0]
CODETHREE[15:8]
CODETHREE[23:16]
CODETHREE[31:24]
These registers contain the PN sequence for symbol "011" and "100". PN code registers are not
affected by hardware or software reset.
Address 30 - 37: I/O expansion port A, write only
Address 30 to 37 are the bit-wise address of bit 0 to 7 of I/O expansion port A. The data bit position of
each bit in the AD bus is the same as if the bit is addressed through the byte-wise address, i.e. bit 7 is
access through AD7 and bit 0 is through AD0.
Address 38 - 3F: I/O expansion port B, write only
Bit-wise address of port B. Access method is the same as port A.
Address 40: I/O expansion port A, write only
This is the byte-wise address of port A. When address 40 is written, all 8 bits of port A are updated at
the same time. This port is not affected by hardware or software reset.
Address 41: I/O expansion port B, write only. default: 11111111
This is the byte-wise address of port B. When address 41 is written, all 8 bits of port B are updated at
the same time. This port is set by hardware reset and is not affected by software reset.
Address 42: I/O expansion port C, read only
Bit 7 to 0 of this register is mapped to the input port PC[7:0]. This port is not affected by hardware or
software reset.
Address 43: I/O expansion port D, read and write. default: 11111111
Bit 7 to 0 of this register is mapped to the I/O port PD[7:0]. When this port is in output mode, write to
this register sets the value of PD pins. When this port is in input mode, the value of PD pins are read
from this location. This port is set by hardware reset and is not affected by software reset.
Address 44: I/O control, port D, write only. default: 11111111
Bit 1 of this register is the I/O control of port D. When it is one, port D is an input port. When it is zero,
port D is an output port and the PD pins are driven by the device. Other bits of this register are
reserved. This register is set by hardware reset and it is not affected by software reset.
Address 46 and 47: General purpose timer, write only. default: 00000000
Register 46 and 47 together form a 16-bit number, GPT_CNT. Register 47 is the upper byte and
register 46 is the lower byte. GPT_CNT determines the cycle time of the GPT output pin in units of
2400 CLK_IN cycle time. If the device operates at 19.2 MHz, GPT cycle time ranges from 125
μ
S to
8.192 sec. GPT always has 50% duty cycle. When GPT_CNT is zero, the GPT output does not
toggle. These registers are cleared by hardware reset and are not affected by software reset.
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