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參數(shù)資料
| 型號(hào)： | W6630CR |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DAC |
| 英文描述： | Stereo Audio DAC(立體聲D/A轉(zhuǎn)換器) |
| 中文描述： | SERIAL INPUT LOADING, 18-BIT DAC, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大小： | 292K |
| 代理商： | W6630CR |
Preliminary W6630CR
- 10 -
The master clock can be either from the ocsillator input or crystal input. If the master clock is from
the oscillator, the external clock must be inputted by XTALI pin and let XTALO pin open. If the master
clock is from the crystal, both side of crystal must be tied between XTALI and XTALO pin and add two
10--20 pF capacitor to DGND at these pins. The XTALO output is inverting with XTALI clock. In
addition, the CLKO pin is buffered and inverting with XTALI input clock.
This device can automatically detect the master clock input frequency by a prescaler circuit to decide
the actual operation clock from 256-times or 384-times sampling clock. When the DAC is start-up
initially such as power-on reset or power-up after hard reset, the steady DAC output will be delay by
about 16 frame sync pulses when the attenuation will be recovered.
When the /RESET pin is held to logic 0, the device will go to initial state. Meanwhile, the DAC
outputs, VOL and VOR, will enter half of AVDD level. Moreover the device is built-in power-on reset
circuit in default. After the reset, the device will work well until the FSLR, sampling clock, is ready.
But this cannot affect the configuration of control registers in the software mode.
7. CONTROL REGISTERS
7.1. Introduction
This device can be controlled either hardware mode or sofware mode by the MODE pin(pin 14). The
differenent functions between the hardware and software mode are listed in Table 7-1, where CR is
control register of the software mode. For example, CR3[0] is the bit 0 of control register 3.
If the pin 14, MODE pin, is low active, the device is selected by the hardware mode. It provides less
functions than ones in the software mode. For hardware mode, only two functions are supported. One
function is the soft mute for DAC output; the other one is the enable or disable the digital de-
emphasis filter. In the hardware mode, the logic-0 presents at the pin18, SSP_EN/MUTE pin, will
force both of DAC into the mute status, and both of DAC will output half of AVDD volts. As for the pin
17 (SSPCLK/DE1 pin) and pin16 (SSPDIN/DE0 pin), these two pins can configure the digital de-
emphasis functions, shown in Table 7-2.
If the pin 14, MODE pin , is hold to logic-1, the device is in the software mode. In the meantime, the
pin18, 17, and 16 become the SSP (Serial Setup Port) control signal. In other word, pin 18 become
the enable signal of SSP; pin 17 becomes the serial latch clock of SSP; and pin 16 becomes the
serial configuration data input of SSP. The control timing is illustrated in Figure 6-3. There are 4
available 16-Bit setup registers can be configured by the SSP port in the software mode. The
functional description of each bit are illustrated in the sections that follow. All 4 registers must be in
write status, not in read status.
FUNCTION
S/W SELECTION
I
2
S, Normal
(CR3[0])
S/W DEFAULT
H/W SELECTION
H/W DEFAULT
Din Input Format
Normal
Normal Only
Normal
Din Input
Resolution
16, 18 Bits
(CR3[2])
16 Bits
16 Bits Only
16 Bits
Frame Pulse
(FSLR) Polarity
L/R = H/L,
L/R = L/H
(CR3[1])
L/R = H/L
L/R = H/L Only
L/R = H/L
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