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參數資料
| 型號： | W6630CR |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DAC |
| 英文描述： | Stereo Audio DAC(立體聲D/A轉換器) |
| 中文描述： | SERIAL INPUT LOADING, 18-BIT DAC, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數： | 12/22頁 |
| 文件大小： | 292K |
| 代理商： | W6630CR |
Preliminary W6630CR
- 12 -
The map of control registers for the software mode is shown in Table 7-4.
CONTROL
REGISTER
CR0
B8
B7
B6
B5
B4
B3
B2
B1
B0
Latch
L-channel
Attenuation
Latch
R-channel
Attenuation
Reserved
AttL[7]
AttL[6]
AttL[5]
AttL[4]
AttL[3]
AttL[2]
AttL[1]
AttL[0]
CR1
AttR[7]
AttR[6]
AttR[5]
AttR[4]
AttR[3]
AttR[2]
AttR[1]
AttR[0]
CR2
Reserved
Reserved
Reserved
ZD
(Zero
Detection)
AG
(Analog
Ground
Control)
AttC
(Atten.
Control)
DE[1]
(De-
emphasis)
DE[0]
(De-
emphasis)
Mute
CR3
Reserved
OTY[3]
(DAC
Output
Type)
OTY[2]
(DAC
Output
Type)
OTY[1]
(DAC
Output
Type)
OTY[0]
(DAC
Output
Type)
WS
(Word
Length
Select)
LRP
(L_chan &
R_chan
Polarity)
DinF
(Din
Input
Format)
Table 7-4 4 x 9-bit Control Registers Map in Software Mode
7.2.1. Control Register 0 (CR0)
This is a 256-step attenuation control register for the left channel. The CR0 register is configured as
0FF in hexdecimal format when the /RESET pin is set to logic zero or power-on reset in default.
B8
B7
B6
B5
B4
B3
B2
B1
B0
CR0
LatchL AttL[7] AttL[6] AttL[5] AttL[4] AttL[3]
AttL[2]
AttL[1]
AttL[0]
LatchL (B8):
This bit controls the attenuation latch for the left channel. If this bit set to logic 1, the device will load
the attenuation value in AttL[7:0] to the device. Otherwise, if this bit is cleared, the AttL[7:0] value will
not affect the attenuation for the left channel.
AttL[7:0] (B[7:0]):
These 8 bits are used to configure the attenuation value for the left channel. The formula of
attenuation level is as follows.
AttL = 20 * log (x/256) dB where x = AttL[7:0], when 0
≤
AttL[7:0]
≤
254
x = 256, when AttL[7:0] = 255 .
When the bit 8, LatchL, is logic-1, the AttL[7:0] value will be loaded into this device and result in the
attenuation in the left channel.
7.2.2. Control Register 1 (CR1)
This is a 256-step attenuation control register for the right channel. The CR1 register is configured as
0FF in hexdecimal format when the RESET pin is set to logic zero or power-on reset in default.
B8
B7
B6
B5
B4
B3
B2
B1
B0
CR1
LatchR AttR[7] AttR[6] AttR[5] AttR[4] AttR[3] AttR[2]
AttR[1] AttR[0]
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W6631 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:STEREO AUDIO DAC |
| W6631CS | 制造商:WINBOND 制造商全稱:Winbond 功能描述:STEREO AUDIO DAC |
| W663HA | 制造商:Eaton Corporation 功能描述:3P CLASS H 60A 600V FUSE BLOCK |
| W6662CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:SCANNER ANALOG FRONT END |
| W66880 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VFD CONTROLLER/DRIVER |
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