
Preliminary W6630CR
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Mute(B0):
This bit is used to control both of DAC to be soft muted. When this bit is set to logic-1, the both of
DAC will be muted.
7.2.4. Control Register 3 (CR3)
This register is used to control the input data format or output type in both of DAC. The CR3 register
becomes the 090 in hexdecimal format when the /RESET pin is set to logic zero or power-on reset in
default.
B8
Res
B7
B6
B5
B4
B3
AttC
B2
WS
B1
LRP
B0
DinF
CR3
OTY[3] OTY[2] OTY[1] OTY[0]
Res (B8):
This bit is reserved bit. It should be logic-zero in the setup.
OTY[3:0](B[7:4]):
These four bits can be used to decide the output type in both of channel as shown in Table 7-6 in the
following.
OTY[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
OTY[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
OTY[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
OTY[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LEFT CHANNEL OUTPUT
Mute
L_chan output
R_chan output
(L_chan + R_chan)/2 output
Mute
L_chan output
R_chan output
(L_chan + R_chan)/2 output
Mute
L_chan output
R_chan output
(L_chan + R_chan)/2 output
Mute
L_chan output
R_chan output
(L_chan + R_chan)/2 output
RIGHT CHANNEL OUTPUT
Mute
Mute
Mute
Mute
L_chan output
L_chan output
L_chan output
L_chan output
R_chan output
R_chan output
R_chan output
R_chan output
(L_chan + R_chan)/2 output
(L_chan + R_chan)/2 output
(L_chan + R_chan)/2 output
(L_chan + R_chan)/2 output
Table 7-6 The Output Type Selection by OTY[3:0] in Control Register CR3
AttC(B3):
This bit is used as the attenuation control bit. When this bit is set to logic-1, the attenuation for both of
channel will be controlled by control register 0(CR0) and ignore the value in control register 1(CR1). If
this bit is cleared, the attenuation is in normal operation. In other word, the control register 0(CR0)
controls the attenuation in left channel; and the control register 1(CR1) controls the attenuation in the
right channel.