- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄363893 > W6630CR (WINBOND ELECTRONICS CORP) Stereo Audio DAC(立體聲D/A轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號(hào)： | W6630CR |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類(lèi)： | DAC |
| 英文描述： | Stereo Audio DAC(立體聲D/A轉(zhuǎn)換器) |
| 中文描述： | SERIAL INPUT LOADING, 18-BIT DAC, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁(yè)數(shù)： | 13/22頁(yè) |
| 文件大小： | 292K |
| 代理商： | W6630CR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)
Preliminary W6630CR
Publication Release Date: December 1998
- 13 -
Revision A1
LatchR (B8):
This bit controls the attenuation latch for the right channel. If this bit set to logic 1, the device will load
the attenuation value in AttR[7:0] to the device. Otherwise, if this bit is cleared, the AttR[7:0] value
will not affect the attenuation for the right channel.
AttR[7:0] (B[7:0]):
These 8 bits are used to configure the attenuation value for the right channel. The formula of
attenuation level is as follows.
AttR = 20 * log (x/256) dB where x = AttR[7:0], when 0
≤
AttR[7:0]
≤
254
x = 256, when AttR[7:0] = 255 .
When the bit 8, LatchR, is logic-1, the AttR[7:0] value will be loaded into this device and result in the
attenuation in the right channel.
7.2.3. Control Register 2 (CR2)
This register controls the zero detection, soft mute and de-emphasis filter. The CR2 register becomes
the 000 in hexdecimal format when the RESET pin is set to logic zero or power-on reset in default.
B8
Res
B7
Res
B6
Res
B5
Res
B4
ZD
B3
AG
B2
DE[1]
B1
DE[0]
B0
CR2
MUTE
Res[8:5] (B[8:5]):
These 4 bits are reserved bits. They should be logic-zero in the setup.
ZD (B4):
This bit control the zero detection status. When this bit is set to logic-1, if the linear data input from
DINLR pin are zero code, this device will force both of DAC to half of AVDD level, i.e., delta-sigma is
disconnected from output amplifier. When this bit is cleared, if the linear data input from DINLR pin
are zero code, this device is general zero output from both of DAC, i.e., delta-sigma is connected to
output amplifier. As for the other input data except for zero code, whether ZD is logic-0 or not, the
DAC output will become normal output.
AG(B3):
This bit controls the level of analog ground for DAC. When this bit is set to logic-1, no matter what the
linear data input from DINLR pin are, this device will force both of DAC to half of AVDD level, I. e.,
delta-sigma is disconnected from output amplifier. When this bit is cleared, if the linear data input
from DINLR pin are zero code, this device is controlled by ZD bit (Bit 4).
DE[1:0](B[2:1]):
These two bits can be used to configure the digital de-emphasis filter as shown in Table 7-5.
DE[1]
0
0
1
1
DE[0]
0
1
0
1
FUNCTION
Disable the digital de-emphasis filter
Enable the digital de-emphasis filter at 48 KHz
Enable the digital de-emphasis filter at 44.1 KHz
Enable the digital de-emphasis filter at 32 KHz
Table 7-5 Digital De-emphasis Filter Configuration in Software Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W6631CS | Stereo Audio DAC(立體聲音頻數(shù)模轉(zhuǎn)換器) |
| W6631 | STEREO AUDIO DAC |
| W6662CF | CCD(Correlated Double Sampler)/CIS(Contact Image Sensors) Analog Front End Signal Processor.(耦合采樣器／接觸圖象傳感器模擬前端信號(hào)處理器) |
| W66880CF | VFD(Vacuum Fluorescent Display) Controller/Driver(VFD驅(qū)動(dòng)器/控制器) |
| W66881CF | VFD(Vacuum Fluorescent Display) Controller/Driver(VFD驅(qū)動(dòng)器/控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W6631 | 制造商:WINBOND 制造商全稱(chēng):Winbond 功能描述:STEREO AUDIO DAC |
| W6631CS | 制造商:WINBOND 制造商全稱(chēng):Winbond 功能描述:STEREO AUDIO DAC |
| W663HA | 制造商:Eaton Corporation 功能描述:3P CLASS H 60A 600V FUSE BLOCK |
| W6662CF | 制造商:WINBOND 制造商全稱(chēng):Winbond 功能描述:SCANNER ANALOG FRONT END |
| W66880 | 制造商:WINBOND 制造商全稱(chēng):Winbond 功能描述:VFD CONTROLLER/DRIVER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。