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參數資料
| 型號： | W6630CR |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DAC |
| 英文描述： | Stereo Audio DAC(立體聲D/A轉換器) |
| 中文描述： | SERIAL INPUT LOADING, 18-BIT DAC, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數： | 17/22頁 |
| 文件大小： | 292K |
| 代理商： | W6630CR |
Preliminary W6630CR
Publication Release Date: December 1998
- 17 -
Revision A1
8.4. Analog Electrical Characteristics
(AVDD = DVDD = +5V, AGND = DGND = 0 volt , Top = 25
°
C; Unless otherwise noted)
PARAMETER
SYM.
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Load Resistance for V
OL
, V
OR
R
LDS
V
OL
, V
OR
5
---
--
KW
Analog Output Range for V
OL
,
V
OR
A
ORS
VOL, VOR @ 0 dB
---
0.62 x
AVDD
---
Vpp
Stereo Analog Ground Output
Voltage for V
AGL
, V
AGR
V
AGS
to AGND
--
0.5 x
AVDD
--
V
Gain Error
G
ES
V
OL
, V
OR
--
±
1
±
30
±
5
---
%FSR
Bipolar Zero Error
Z
DE
---
---
mV
8.5. Digital Switching Characteristics
8.5.1 Stereo Input Data Timing
(DVDD = AVDD = 5
±
5%V; AGND = DGNDD = 0V; all digital circuits referenced to DGND; Top = +25
°
C)
PARAMETER
SYM.
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reset Pulse Width
T
RPW
RESET
20
---
---
nS
Master Clock Frequency at
384 x FSLR
T
MC3
XTALI, XTALO
12.288
16.9344
18.432
MHz
Master Clock Frequency at
256 x FSLR
T
MC2
XTALI, XTALO
8.192
11.2896
12.288
MHz
Frame Sync. Frequency for
Stereo
T
FS
FSLR
32
44.1
48
KHz
Clock Duty Cycle
T
DC
XTALI, XTALO
30
50
70
%
Bit Clock Frequency
T
BC
BCLK
---
---
10
MHz
Bit Clock Pulse Width at
LOW or HIGH
T
BCW
BCLK
50
---
--
nS
Receive Sync. Timing
T
RE
T
ER
BCLK Rising -->
FSLR Edge
FSLR Edge -->
BCLK Rising
30
30
---
---
---
---
nS
Setup Time for DINLR Valid
T
STD
Refer to BCLK
rising
30
---
---
nS
Hold Time for DINLR Valid
T
HTD
Refer to BCLK
rising
30
---
---
nS
Note: these parameters are shown in Figure 8-1, 8-2 and 8-3
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