
Preliminary W6630CR
Publication Release Date: December 1998
- 15 -
Revision A1
WS(B2):
This bit is the input word length selection. When this bit is set to logic-1, the linear input data from
DINLR(pin5) selects 18 Bit format. If the bit is cleared, the one will selects the 16-bit data format
LRP(B1):
This bit is used to control the polarity of sampling clock(FSLR pin). Note this bit only affects the
normal data format and is ignored by I
2
S data format. When this bit is set to logic-1, the left channel
corresponds to the low state in FSLR pin and the right channel is located at the high state in FSLR
pin. When the bit is cleared, the polarity of FSLR pin is reversed.
DinF(B0):
This bit is used to control the input data format from the normal or I
2
S format. When this bit is set to
logic-1, the input data format is the I
2
S format. Otherwise it will become the normal data input.
8. ELECTRICAL CHARACTERISTICS
8.1. Absolute Maximum Ratings
(Voltage Referenced to DGND and AGND pin)
PARAMETER
SYMBOL
AVDD, DVDD
AVDD
DVDD
---
---
T
OP
T
STG
RATING
-0.3 to +6.5
±
0.1
-0.3 to AVDD +0.3
-0.3 to DVDD +0.3
-25 to +85
-85 to +85
UNIT
V
V
V
V
°
C
°
C
Power Supply Voltage
Analog V
DD
to Digital V
DD
Difference
Analog Output Voltage
Digital Input/Output Voltage
Operating Temperature
Storage Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
8.2. DC Characteristics
(AGND = DGND = 0 volt; TOP = -25 to +85
°
C)
PARAMETER
Operating Voltage
SYMBOL
AVDD,
DVDD
Iop
CONDITION
----
MIN.
2.7
TYP.
5.0
MAX.
5.25
UNIT
V
Operating Current
AVDD = DVDD = +5 V,
XTALI = 16.934 MHz
All digital input pins
except for ssp_en,
sspclk, mode, reset
---
--
50
mA
Input High Voltage
V
IH1
2.0
---
-----
V