
Preliminary W6630CR
Publication Release Date: December 1998
- 11 -
Revision A1
Continued
FUNCTION
De-emphasis
Control
S/W SELECTION
32K, 44.1K, 48K,
and Off
(CR2[2:1])
8 Bits attenuation
for L/R Channel
(L:CR0[7:0])
(R:CR1[7:0])
Yes
(CR2[0])
Yes
(CR2[4])
Yes
(CR3[7:4])
S/W DEFAULT
Off
H/W SELECTION
32K, 44.1K, 48K,
and Off
(Pin17, Pin 16)
Not Support
H/W DEFAULT
Off
L/R Attenuation
Control
0 dB
0 dB
Mute Control
Off
Yes
Off
Zero Detection
Off
Not Support
Off
Channel Ouput
Type Control
L_chan = L
R_chan = R
Not Support
L_chan = L
R_chan = R
Table 7-1. The Comparison between the Software Mode and Hardware Mode
PIN 17(DE1)
0
0
1
1
PIN 16(DE0)
0
1
0
1
FUNCTION
Disable the digital de-emphasis filter
Enable the digital de-emphasis filter at 48 KHz
Enable the digital de-emphasis filter at 44.1 KHz
Enable the digital de-emphasis filter at 32 KHz
Table 7-2 Digital De-emphasis Filter Configuration in Hardware Mode
7.2. Control Registers in Software Mode
There are 4x9-bit registers for controlling the chip in the software mode. These registers are labeled
CR0 to CR3. The descriptions are as follows. Note that "setting" is corresponding to logic "1" and
"clearing" is corresponding to logic "0". In addition, the res bit indicates the reserved bit and must be
logic-0. Because the first 5 bits are res bit and the data must be logic-0; the next 2 bits are address
bits, A1 and A0 to select control register shown in Table 7-3; the final 9 bits are the actual configured
data input bits. The following control register only show how to control the configured data bits. In
other word, the control register only show Bit[9:0]. The detail timing is shown in the Figure 6-3.
A1
0
0
1
1
A0
0
1
0
1
CONTROL REGISTER SELECTION
Select Control register 0 (CR0)
Select Control register 1 (CR1)
Select Control register 2 (CR2)
Select Control register 3 (CR3)
Table 7-3 Control Register Selection