
Preliminary W6630CR
Publication Release Date: December 1998
- 19 -
Revision A1
7.5.2. Serial Setup Port (SSP) Timing, continued
PARAMETER
SYM.
T
SPRF
CONDITIONS
SSPCLK Rising -->
SSP_EN Falling Edge
SSP_EN Falling -->
SSPCLK Rsiing
SSP_EN
MIN.
30
TYP.
---
MAX.
---
UNIT
nS
SSP Latch Timing
T
SPFR
30
---
---
SSP Latch Pulse Width
T
LPW
30
--
---
nS
SSP Hold High after Latch
T
LPH
SSP_EN
30
---
---
nS
SSPDIN Setup Time
T
SST
Refer to SSPCLK rising
30
---
---
nS
SSPDIN Hold Time
T
SHT
Refer to SSPCLK rising
30
---
---
nS
(DVDD = AVDD = 5
±
5% V; AGND = DGNDD = 0V; all digital circuits referenced to DGND; Top = +25
°
C)
Note: these parameters are shown in Figure 8-4
SSP_EN/MUTE
SSPCLK/DE1
SSPDIN/DE0
TSPC
TSPCWTSPCW
TLPW
TLPH
TSPRF
TSST
TSHT
Figure 8-4 Serial Setup Port (SSP) Timing
9. APPLICATION INFORMATION
This device has two power supply. One is the digital power (DVDD); the other is the analog power
(AVDD). The positive value is supplied from 2.7 to 5.25 volt. If this device is used as two power
supply, the user had better add two diodes between the AVDD and DVDD pin as shown in Figure 9-1
in order to avoid occurring the latch-up condition. The latch-up circuit can be ignored if the two power
supply are connected in common area.
The application circuit is referred to Figure 9-1 as follows. It uses the crystral as the master clock
input. Therfore, the XTALO pin must be tied. If the oscillator input is used, the XTALO pin is opened,
and is inputted to XTALI pin. The audio data input source can be either from digital output of CD
player via digital audio interface or user design system. If user selects the software mode, the
configuration value may be from the micro-processor via the serial setup port (SSP). As for the ZERO
pin, it is the open-drain output pin. User must add a pull-up resistor about 1K
to ZERO pin .