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參數資料
| 型號： | W6630CR |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DAC |
| 英文描述： | Stereo Audio DAC(立體聲D/A轉換器) |
| 中文描述： | SERIAL INPUT LOADING, 18-BIT DAC, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數： | 5/22頁 |
| 文件大小： | 292K |
| 代理商： | W6630CR |
Preliminary W6630CR
Publication Release Date: December 1998
- 5 -
Revision A1
6. FUNCTIONAL DESCRIPTIONS
Figure 5 illustrates the functional blocks of the Winbond's stereo 16 or 18 bit audio DAC .
6.1. Power Supply Management System
6.1.1. Power Supply for All Analog Signals Processing
All analog circuits are supplied with AVDD from +2.7 volt to 5.25 volt, typically +5 volt. In addition, the
AVDD pin should be decoupled to AGND pin with a 0.1
μ
F capacitor.
6.1.2. Power Supply for All Digital Signals Processing
All digital circuits are supplied with DVDD from +2.7 volt to 5.25 volt, typically +5 volt. In addition, the
DVDD pin should be decoupled to DGND pin with a 0.1 uF capacitor.
6.1.3. Analog Signal Ground Voltage Control System
The analog ground output for the left channel refers to VAGL pin, typically half of AVDD. Moreover
the analog ground output for the right channel refers to VAGR pin, typically half of AVDD. These two
pin should be connected to AGND pin with a 10
μ
F capacitor.
6.2. Delta-Sigma DAC-Filter
This device has built in stereo linear 16 or 18-bit D/A converter (DAC)- filter based on the delta-sigma
technology. The linear input data from DINLR pin including the left and right channel are fed into the
8-times interpolation filter with -40 dB stop band attenuation and +- 0.15 dB ripple in the pass band,
shown in Figure 6-1. Then the filtered data is quantized by 64-time oversampling multi-bit delta-sigma
modulator whether the sampling rate is 256-times or 384-times sampling clock rate. The modulator is
a 3rd-order noise shaper with multi-level amplitude quantizer. The structure is shown in Figure 6-2.
And the quantization noise performance of the multi-level modulator is shown in Figure 6-3.The the
quantized values are passed into the analog DAC for the left and right channel separtedly. Finally, the
data are sented the analog low pass filter and output amplifer to generate the analog signal output at
the VOL pin for the left channel , and at the VOR pin for the right channel.
6.3. Data Conversion
This block is the digital data conversion circuit. It consists of serial data port (SDP), serial setup port
(SSP) with 4 x 9 registers, and mode function control block.
6.3.1. Serial Data Port (SDP)
This SDP block will convert the data input from DINLR pin into parallel data, separated into the left
and right channel, depended on I
2
S or normal data input format and 384-times or 256-times sampling
clock rate. The timing diagram are shown in Figure 6-5 and 6-6. In the I
2
S format, the data is
compatible with Philips serial data protocol, the MSB bit is shifted into SDP block at the rising edge of
second BCLK, and the following data bit are shifted into the SDP port at the following rising edge of
sequence BCLK. Moreover when the FSLR is in low, the input data is corresponding to the left
channel; and when the FSR is logic-1, the input data is corresponding to the right channel. For the
normal format, the LSB bit is justified to the transition of FSLR pin, and the MSB bit is the first bit
presented on the input data sequence. The data are latched into the SDP port same as the I
2
S format
at the rising edge of BCLK. But the left or right channel input location is reversed with I
2
S format. In
other word, the logic-one in the FSLR is the left channel data; and the logic-zero in the FSLR pin is
the right channel data for the Normal data format. The FSLR pin is the sampling clcok rate. For this
device, it should be 32K, 44.1K or 48 KHz input. All input data, whether is 16 or 18 bit, are 2's
complement.
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相關代理商/技術參數 |
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|---|---|
| W6631 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:STEREO AUDIO DAC |
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| W663HA | 制造商:Eaton Corporation 功能描述:3P CLASS H 60A 600V FUSE BLOCK |
| W6662CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:SCANNER ANALOG FRONT END |
| W66880 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VFD CONTROLLER/DRIVER |
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