
W9961CF
- 3 -
TABLE OF CONTENTS
1 GENERAL DESCRIPTION.....................................................................................................................7
2 FEATURES...............................................................................................................................................8
3 PIN CONFIGURATION ........................................................................................................................ 10
4 PIN DESCRIPTION............................................................................................................................... 11
4.1 P
IN
D
EFINITION
........................................................................................................................................ 11
4.2 P
IN
L
IST
................................................................................................................................................... 17
4.3 P
OWER
O
N
R
ESET
I
NITIALIZATION
............................................................................................................. 22
5 SYSTEM DIAGRAM............................................................................................................................. 24
6 BLOCK DIAGRAM............................................................................................................................... 26
7 FUNCTIONAL DESCRIPTION............................................................................................................ 27
7.1 VPRE P
ROCESSOR
.................................................................................................................................... 27
7.2 V
IDEO
C
ODEC
........................................................................................................................................... 28
7.2.1 Video Coding.................................................................................................................................... 28
7.2.1.1 I-pictures INTRA Coding.............................................................................................................................28
7.2.1.2 P-pictures INTER Coding ............................................................................................................................29
7.2.1.3 P-pictures INTRA Coding............................................................................................................................29
7.2.2 Video Decoding ................................................................................................................................ 29
7.3 VPOST P
ROCESSOR
................................................................................................................................. 30
7.3.1 Video Post-processing....................................................................................................................... 30
7.3.2 Display Control ................................................................................................................................ 31
7.3.3 Video Output Control........................................................................................................................ 31
7.3.3.1 Hue, Saturation, Contrast, and Brightness Adjustments................................................................................31
7.3.3.2 Video Output Interface.................................................................................................................................32
7.4 RISC M
ICROPROCESSOR
........................................................................................................................... 35
7.4.1 RISC Pipeline Stages ........................................................................................................................ 35
7.4.2 Address Spaces ................................................................................................................................. 36
7.4.2.1 Program Memory Address Space..................................................................................................................36
7.4.2.2 Data Memory Address Space.......................................................................................................................36
7.4.3 RISC Registers.................................................................................................................................. 38
7.4.3.1 General Registers ........................................................................................................................................38
7.4.3.2 Shadow Registers ........................................................................................................................................38
7.4.4 RISC Interrupt Handling................................................................................................................... 39
7.5 INTC (I
NTERRUPT
C
ONTROLLER
).............................................................................................................. 41
7.6 T
IMER
...................................................................................................................................................... 43
7.7 FDMA C
ONTROLLER
................................................................................................................................ 44
7.7.1 FDMA Transfer Modes ..................................................................................................................... 45
7.7.2 FDMA Transfer Types....................................................................................................................... 45