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參數(shù)資料
| 型號： | W9961CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | H.263/H.261 Video Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | 28 X 28 MM, 2.60 MM HEIGHT, PLASTIC, QFP-208 |
| 文件頁數(shù)： | 44/65頁 |
| 文件大小： | 344K |
| 代理商： | W9961CF |
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W9961CF
- 44 -
7.7 FDMA Controller
Write Data
Machine
State
Queue
DREQ[11:0]
Mask
DMA
S/W
ACK
ENG
Temp
Read Data
Video Memory
DACK_[11:0]
Figure 7.12 FDMA Controller Block Diagram
The FDMA controller supports 12 channels that are used for direct memory access between video
memory and hardware engines. The RISC first sets up the FDMA registers, which contain picture
start, engine start, picture size, and transfer size. A 16-level request queue is used to buffer request
from each FDMA channel. Once the DMA transfer is complete, the controller interrupts the RISC. In
addition to accept requests from hardware engines, the FDMA also responds to request that are
initiated by software. Software may initiate a DMA service request by programming a channel value
into the Software FDMA register. Software FDMA has the highest priority and will be serviced
immediately when the FDMA engine is ready. FDMA channels are listed in Table 7.6.
Table 7.6 FDMA Channels
Channel
0
1
2
3
4
5
6
7
8
9
A
B
Note 1. R: engines to video memory; W: video memory to engines.
Engine
MC
ME
ME
MC
DCT/IDCT
DCT/IDCT
DCT/IDCT
PIO
PIO
PIO
DBF
ME
Addressing
Mode
R/W
W
W
W
R
W
R
R
W
W
R/W
R/W
R
Description
Block In for MC
Block In for Search Window of ME
Block In for Current Macro Block
Block Out for By-Pass Filter
Block In for DCT
Block Out for Decoder Re-Construct
Block Out for Encoder Re-Construct
BCH Encoder Bitstream In
Decoder Bitstream In
Encoder Bitstream In/Out, BCH Out
Deblocking Filter Data In/Out
Block Out for Predicted Macro Block
Linear
Linear
Linear
Demand
Demand
Demand
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