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參數資料
| 型號： | W9961CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | H.263/H.261 Video Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | 28 X 28 MM, 2.60 MM HEIGHT, PLASTIC, QFP-208 |
| 文件頁數： | 45/65頁 |
| 文件大小： | 344K |
| 代理商： | W9961CF |
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W9961CF
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7.7.1 FDMA Transfer Modes
The FDMA supports two transfer modes: Block and Demand. A 16-level request queue is used to
buffer request from each FDMA channel. Each channel has associated with it a mask bit which can
be set to disable the incoming DREQ. An unrestricted mode is also supported when the picture start is
out of picture boundary, where an edge pixel is used instead.
In Block Transfer mode the FDMA is activated by DREQ to continue making transfers during the
service until a TC is encountered. The FDMA ignores DREQ of that channel during the service.
In Demand Transfer mode the FDMA is activated by DREQ to continue making transfers during the
service until a TC is encountered, or until DREQ goes inactive. Thus transfers may continue until the
hardware engine has exhausted its data capacity. After the hardware engine has had a chance to
catch up, the FDMA service is reestablished by means of a DREQ. During the time between services,
the intermediate values of address and word count are stored in the temporary registers.
7.7.2 FDMA Transfer Types
Two transfer types are supported: Read and Write. Read transfers move data from a hardware engine
to video memory. Write transfers move data from video memory to a hardware engine.
7.7.3 FDMA Programming
The FDMA supports two addressing modes: Block and Linear. Normally, Block addressing is used by
Block Transfer modes, and Linear addressing is by Demand Transfer modes.
Block Transfer Mode with Block Addressing Programming
Refer to Figure 7.13. Programming sequence is:
1. FDMA Mode register: LIN = 0, DMD = 0, R/W_ = 0 or 1
2. Transfer Size registers: EW = 3, EH = 3, transfer size = (EW
+
1)
×
(EH
+
1) = 16
3. Picture Size registers: PW = 9, PH = 9
4. Frame Memory Start Address: FMSA = 64, physical memory start address (DWORD) = 64
×
64
/
4 =
1024
5. Picture Start registers: PSX = 3, PSY = 2
6. Start to calculate finit = PSY
×
( PW+1) + PSX + FMSA = 2
×
( 9+1 ) + 3 + 1024 = 1047
7. Engine Start registers: ESX = 1, ESY = 1
8. Enable DMASK
Demand Transfer Mode with Linear Addressing Programming
Refer to Figure 7.14. Programming sequence is:
1. FDMA Mode register: LIN = 1, DMD = 1, R/W_ = 0 or 1
2. Transfer Size registers: EW = 100, EH = 1, transfer size = EH
×
2
9
+
(EW
+
1) = 613
3. Picture Size registers: PW = 9, PH = 9
4. Frame Memory Start Address: FMSA = 64, physical memory start address (DWORD) = 64
×
64
/
4 =
1024
5. Picture Start registers: PSX = 15, PSY = 1
6. Start to calculate finit = PSY
×
( PW+1) + PSX + FMSA = 1
×
( 9+1 ) + 15 + 1024 = 1049
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