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參數(shù)資料
| 型號： | W9961CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | H.263/H.261 Video Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | 28 X 28 MM, 2.60 MM HEIGHT, PLASTIC, QFP-208 |
| 文件頁數(shù)： | 39/65頁 |
| 文件大小： | 344K |
| 代理商： | W9961CF |
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W9961CF
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Depth of the shadow registers is two, which enables a nested interrupt in a CALL subroutine.
7.4.4 RISC Interrupt Handling
There are 31 interrupt vectors stored on top of the PM, each points to the entry of an interrupt service
routine. The first 15 interrupt vectors (0001H~00FH) are used for engine interrupts. The last 16
interrupt vectors (0010H~001FH) are used for DMA TC interrupts. These interrupt vectors are shown
in Table 7.4.
Table 7.4 RISC Interrupt Vectors
Vector
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
Engine
Description
Main program starting address
ME complete interrupt
MC complete interrupt
IDCT complete interrupt
DCT complete interrupt
Video capture complete interrupt
Pre-filter complete interrupt
VLE FIFO full interrupt
TIMER DTR interrupt
TIMER ETR interrupt
TIMER TR interrupt
Post-filter complete interrupt
Deblocking filter complete interrupt
VLD complete interrupt
BCH frame un-lock, Encode Output FIFO full, Encode Input FIFO
empty, or Decode Input FIFO empty interrupt (Note 1)
VLD run-level block error interrupt
DMA TC interrupt for MC input
DMA TC interrupt for Search Window
DMA TC interrupt for Current Macro Block
DMA TC interrupt for MC output
DMA TC interrupt for DCT input
DMA TC interrupt for IDCT output of Decoding
DMA TC interrupt for IDCT output of Encoding
DMA TC interrupt for Encoding bitstream
DMA TC interrupt for Decoding bitstream
DMA TC interrupt for bitstream from PCI FIFO
DMA TC interrupt for deblocking filter data in/out
DMA TC interrupt for Predicted Macro Block
Reserved
ME
MC
DCT/IDCT (D)
DCT/IDCT (E)
VPRE
VPRE
VLE
TIMER
TIMER
TIMER
VPOST
DBF
VLPIO
VLPIO
000FH
0010H
0011H
0012H
0013H
0014H
0015H
0016H
0017H
0018H
0019H
001AH
001BH
001AH ~ 001FH
Note 1. Controlled by bits 11-8 of the PIO Control register (PIOCR).
VLPIO
MC
ME
ME
MC
DCT/IDCT
DCT/IDCT
DCT/IDCT
VLPIO
VLPIO
VLPIO
DBF
ME
When an interrupt occurs, program counter jumps to the interrupt service routine pointed by the
corresponding interrupt vector. RISC also disables the other interrupt inputs and stores current
program counter, instruction, and execution status at IF, DEC, and EXE stages into the shadow
registers.
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