
Preliminary W742C810
Publication Release Date: May 1999
- 11 -
Revision A1
directly or indirectly. However, the data bank must be confirmed first; the page in the data bank will
be done in the indirect addressing mode, too. In indirect addressing mode, each data bank will be
divided into eight pages. Before the data memory is addressed indirectly, the page which the data
memory is located in must be confirmed. The organization of the data memory is shown in Figure 6-
2.
1st data bank
(or Working Registers bank)
1024
address
000H
:
07FH
080H
:
0FFH
4 bits
1024 * 4 bits
2nd data bank
(or Working Registers bank)
:
:
:
380H
:
3FFH
8th data bank
00H
:
0FH
10H
:
1FH
20H
:
2FH
70H
:
7FH
:
:
1st data RAM page
(or 1st WR page)
2nd data RAM page
(or 2nd WR page)
8th data RAM page
(or 8th WR page)
3rd data RAM page
(or 3rd WR page)
Figure 6-2 Data Memory Organization
The 1st and 2nd data bank (00H to 7FH & 80H to FFH) in the data memory can also be used as the
working registers (WR). This is also divided into sixteen pages. Each page contains 16 working
registers. When one page is used as WR, the others can be used as the normal data memory. The
WR page can be switched by executing the MOV WRP,R or MOV WRP,#I instruction. The data
memory cannot operate directly with immediate data, but the WR can do so. The relationship
between data memory locations and the page register (PAGE) in indirect addressing mode is
described in the next sub-section.
6.4.2 Page Register (PAGE)
The page register is organized as a 4-bit binary register. The bit descriptions are as follows:
R/W
R/W
R/W
0
1
2
3
PAGE
Note: R/W means read/write available.
Bit 3 is reserved.
Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits in one data bank:
000 = Page 0 (00H - 0FH)
001 = Page 1 (10H - 1FH)
010 = Page 2 (20H - 2FH)
011 = Page 3 (30H - 3FH)
100 = Page 4 (40H - 4FH)
101 = Page 5 (50H - 5FH)
110 = Page 6 (60H - 6FH)
111 = Page 7 (70H - 7FH)