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參數資料
| 型號： | W742C810 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT MICROCONTROLLER |
| 中文描述： | 4-BIT, MROM, 3.58 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, QFP-100 |
| 文件頁數： | 13/42頁 |
| 文件大小： | 501K |
| 代理商： | W742C810 |
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Preliminary W742C810
Publication Release Date: May 1999
- 13 -
Revision A1
6.5 Accumulator (ACC)
The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data
between the memory, I/O ports, and registers.
6.6 Arithmetic and Logic Unit (ALU)
This is a circuit which performs arithmetic and logic operations. The ALU provides the following
functions:
Logic operations: ANL, XRL, ORL
Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,
SKB3
Shift operations: SHRC, RRC, SHLC, RLC
Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC
After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is
stored in the internal registers. CF can be read out by executing MOV R, CF.
6.7 Main Oscillator
The W742C810 provides a crystal oscillation circuit to generate the system clock through external
connections. The 3.58 MHz crystal must be connected to XIN1 and XOUT1, and a capacitor must be
connected to XIN1 and VSS if an accurate frequency is needed.
XIN1
XOUT1
Crystal
3.58MHz
Figure 6-3 System clock oscillator Configuration
6.8 Sub-Oscillator
The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, only the
32768 Hz crystal can be connected to XIN2 and XOUT2, and a capacitor must be connected to XIN2
and V
SS
if an accurate frequency is needed. The sub-oscillator will be oscillatory continuously in
STOP mode.
6.9 Dividers
Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts.
When the main oscillator starts action, the Divider0 is incremented by each clock (F
OSC
). When an
overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable
flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been
set (HEF.0 = 1), the hold state is terminated. The last 4-stage of the Divider0 can be reset by
executing CLR DIVR0 instruction. If the main oscillator is connected to the 32768 Hz crystal, the
EVF.0 will be set to 1 periodically at the period of 500 mS.
If the sub-oscillator starts action, the Divider1 is incremented by each clock (Fs). When an overflow
occurs, the Divider1 event flag is set to 1 (EVF.4 = 1). Then, if the Divider1 interrupt enable flag has
been set (IEF.4 = 1), the interrupt is executed, while if the hold release enable flag has been set
(HEF.4 = 1), the hold state is terminated. The last 4-stage of the Divider1 can be reset by executing
CLR DIVR1 instruction. The same as with EVF.0, the EVF.4 is set to 1 periodically. However, there
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