
Preliminary W742C810
- 18 -
Bit 0 = 0 The internal fundamental frequency of Timer 1 is F
OSC
.
= 1 The internal fundamental frequency of Timer 1 is F
OSC
/64.
Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.
= 1 The fundamental frequency source of Timer 1 is the sub-oscillator frequency FS
(32.768 KHz).
Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP pin.
= 1 The specified frequency of Timer 1 is delivered at MFP pin.
Bit 3 = 0 Timer 1 stops down-counting.
= 1 Timer 1 starts down-counting.
6.13 Interrupts
The W742C810 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and
one external interrupt source (port RC). Vector addresses for each of the interrupts are located in the
range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to
control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF
have been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts
are inhibited until the EN INT or MOV IEF,#I instruction is invoked. The interrupts can also be
disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold
mode will be released momentarily and interrupt subroutine will be executed. After the RTN
instruction is executed in an interrupt subroutine, the
μ
C will enter hold mode again. The operation
flow chart is shown in Figure 6-9. The control diagram is shown below.
S
R
Q
S
R
Q
IEF.0
IEF.1
Interrupt
Process
Circuit
Interrupt
Vector
Generator
004H
008H
014H
IEF.2
S
R
Q
Initial Reset
MOV IEF, #I
Enable
EN INT
EVF.1
EVF.0
EVF.2
Initial Reset
CLR EVF, #I instruction
DIS INT instruction
Disable
Divider 0
overflow signal
Timer 0
underflow signal
Port RC
signal change
S
R
Q
S
R
Q
Timer 1
underflow signal
IEF.4
EVF.4
IEF.7
EVF.7
00CH
020H
Divider 1
overflow signal
Figure 6-8 Interrupt event control duagram