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參數資料
| 型號： | W742C810 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT MICROCONTROLLER |
| 中文描述： | 4-BIT, MROM, 3.58 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, QFP-100 |
| 文件頁數： | 15/42頁 |
| 文件大小： | 501K |
| 代理商： | W742C810 |
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Preliminary W742C810
Publication Release Date: May 1999
- 15 -
Revision A1
6.11 Watchdog Timer (WDT)
The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from
unknown errors. When the corresponding option code bit of the WDT set to 1, the WDT is enabled,
and if the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is
F
OSC
/2048. The input clock of the WDT can be switched to F
OSC
/16384 (or F
OSC
/2048) by setting
SCR.2 to 1 (or clearing SCR.2 to 0). The contents of the WDT can be reset by the instruction CLR
WDT. In normal operation, the application program must reset WDT before it overflows. A WDT
overflow indicates that operation is not under control and the chip will be reset. The WDT overflow
period is 1S when the system clock (F
OSC
) is 32 KHz and WDT clock input is F
OSC
/2048. When the
corresponding option code bit of the WDT set to 0, the WDT function is disabled. The organization of
the Divider0 and watchdog timer is shown in Figure 6-5.
Q1
Q2
Q9
Q10 Q11 Q12
Q14
Q13
Fosc
S
R
Q
HEF.0
IEF.0
1. Reset
2. CLR EVF,#01H
3. CLR DIVR0
EVF.0
Hold mode release (HCF.0)
Divider interrupt (INT0)
...
Overflow signal
WDT
Enable
Disable
SCR.2
Fosc/2048
Fosc/16384
Option code is reset to "0"
Qw1
R
Qw2
R
Qw4
R
Qw3
R
Divider0
System Reset
1. Reset
2. CLR WDT
Option code is set to "1"
Figure 6-5 Organization of Divider0 and watchdog timer
6.12 Timer/Counter
6.12.1 Timer 0 (TM0)
Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into
TM0 by executing the MOV TM0L(TM0H),R instructions. When the MOV TM0L(TMOH),R instructions
are executed, it will stop the TM0 down-counting (if the TM0 is down-counting) and reset the MR0.3 to
0, and the specified value can be loaded into TM0. We can then set MR0.3 to 1; this will cause the
event flag 1 (EVF.1) to be reset, and the TM0 will start to count. When it decrements to FFH, Timer 0
stops operating and generates an underflow (EVF.1 = 1). Then, if the Timer 0 interrupt enable flag
has been set (IEF.1 = 1), the interrupt is executed, while if the hold release enable flag 1 has been set
(HEF.1 = 1), the hold state is terminated. The Timer 0 clock input can be set as F
OSC
/1024 or F
OSC
/4
by setting MR0.0 to 1 or resetting MR0.0 to 0. The default timer value is F
OSC
/4. The organization of
Timer 0 is shown in Figure 6-6.
If the Timer 0 clock input is F
OSC
/4:
Desired Timer 0 interval = (preset value +1)
×
4
×
1/ F
OSC
If the Timer 0 clock input is F
OSC
/1024:
Desired Timer 0 interval = (preset value +1)
×
1024
×
1/ F
OSC
Preset value: Decimal number of Timer 0 preset value
F
OSC
: Clock oscillation frequency
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