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參數資料
| 型號： | W742C810 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT MICROCONTROLLER |
| 中文描述： | 4-BIT, MROM, 3.58 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 2.75 MM HEIGHT, QFP-100 |
| 文件頁數： | 14/42頁 |
| 文件大小： | 501K |
| 代理商： | W742C810 |
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Preliminary W742C810
- 14 -
are two period times (125 mS & 500 mS) that can be selected by setting the SCR.3 bit. When SCR.3
= 0 (default), the 500 mS period time is selected; SCR.3 = 1, the 125 mS period time is selected.
6.10 Dual-clock operation
In the dual-clock mode, the clock source of the LCD frequency selector should be the sub-oscillator
clock (32768 Hz) only. So when the STOP instruction is executing, the LCD will keep working in the
dual-clock mode.
In this dual-clock mode, the normal operation is performed by generating the system clock from the
main-oscillator clock (Fm). The slow operation can be performed as required by generating the
system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow
operation is performed by resetting or setting the bit 0 of the System clock Control Register (SCR). If
the SCR.0 is reset to 0, the clock source of the system clock generator is main-oscillator clock; if the
SCR.0 is set to 1, the clock source of the system clock generator is sub-oscillator clock. In the dual-
clock mode, the main-oscillator can stop oscillating when the STOP instruction is executing or the
SCR.1 is set to 1.
When the SCR is set or reset, we must be careful in the following cases:
1. X000B
→
X011B: we should not exchange the F
OSC
from Fm into Fs and disable Fm
simultaneously. We can first exchange the F
OSC
from Fm into Fs, then disable the main-oscillator.
So the order should be X000B
→
X001B
→
X011B.
2. X011B
→
X000B: we should not enable Fm and exchange the F
OSC
from Fs into Fm
simultaneously. We can first enable the main-oscillator; the 2nd step is calling a delay subroutine
to wait until the main-oscillator is oscillating stably; then the last step is to exchange the F
OSC
from
Fs into Fm. So the order should be X011B
→
X001B
→
delay the Fm oscillating stably time
→
X000B.
We must remember that the X010B state is inhibitive, because it will induce the system shutdown.
The organization of the dual-clock operation mode is shown in Figure 6-4.
System Clock
Generator
T1
T2
T3
T4
Main Oscillator
XIN1
XOUT1
Sub-oscillator
XIN2
XOUT2
Fosc
Divider 0
SCR: System clock Control Register ( default = 00H )
Bit0
Bit1
Bit2
Bit3
0 : Fosc = Fm
0 : Fm enable
0 : WDT input clock is Fosc/2048
1 : WDT input clock is Fosc/16384
Fm
Fs
enable/disable
SCR.1
STOP
HOLD
SCR.0
LCD Frequency
Selector
F
LCD
Divider 1
INT4
HCF.4
SCR.3(14/12 bit)
0 : 14 bit
Daul clock operation mode:
- SCR.0 = 0, Fosc = Fm; SCR.0 = 1, Fosc = Fs
- Flcd = Fs, In STOP mode LCD work continue.
Figure 6-4 Organization of the dual-clock operation mode
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