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參數(shù)資料
| 型號(hào)： | W79E648 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Fast 8051 Compatible microcontroller with a redesigned Processor |
| 中文描述： | 快速8051兼容微控制器重新設(shè)計(jì)的處理器 |
| 文件頁數(shù)： | 12/80頁 |
| 文件大小： | 407K |
| 代理商： | W79E648 |
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Preliminary W79E648
- 12 -
PD:
Setting this bit causes the W79E648 to go into the POWER DOWN mode. In this mode all the
clocks are stopped and program execution is frozen.
Setting this bit causes the W79E648 to go into the IDLE mode. In this mode the clocks to the
CPU are stopped, so program execution is frozen. But the clock to the serial, timer and
interrupt blocks is not stopped, and these blocks continue operating.
IDL:
Timer Control
Bit:
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Mnemonic: TCON
Address: 88h
TF1:
Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when
the program does a timer 1 interrupt service routine. Software can also set or clear this bit.
TR1:
Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.
TF0:
Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when
the program does a timer 0 interrupt service routine. Software can also set or clear this bit.
TR0:
Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off.
IE1:
Interrupt 1 edge detect: Set by hardware when an edge/level is detected on
INT1
. This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
IT1:
Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
IE0:
Interrupt 0 edge detect: Set by hardware when an edge/level is detected on
INT0
. This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
IT0:
Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
Timer Mode Control
Bit:
7
6
5
4
3
2
1
0
GATE
C T
/
M1
M0
GATE
C T
/
M1
M0
TIMER1
TIMER0
Mnemonic: TMOD
Address: 89h
GATE: Gating control: When this bit is set, Timer/counter x is enabled only while
INTx
pin is high and
TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set.
C T
/
: Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When set
, the timer counts high-to-low edges of the Tx pin.
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