
Preliminary W79E648
Publication Release Date: 05/31/2004
- 69 - Revision A1
17.3.2 MOVX Characteristics Using Strech Memory Cycle
PARAMETER
SYMBOL
VARIABLE
CLOCK
MIN.
VARIABLE
CLOCK
MAX.
UNITS
STRECH
Data Access ALE Pulse Width
t
LLHL2
1.5t
CLCL
- 5
2.0t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
Address Hold After ALE Low for
MOVX write
t
LLAX2
0.5t
CLCL
- 5
nS
RD
Pulse Width
t
RLRH
2.0t
CLCL
- 5
t
MCS
- 10
nS
t
MCS
= 0
t
MCS
>0
WR
Pulse Width
t
WLWH
2.0t
CLCL
- 5
t
MCS
- 10
nS
t
MCS
= 0
t
MCS
>0
RD
Low to Valid Data In
t
RLDV
2.0t
CLCL
- 20
t
MCS
- 20
nS
t
MCS
= 0
t
MCS
>0
Data Hold after Read
t
RHDX
0
nS
Data Float after Read
t
RHDZ
t
CLCL
- 5
2.0t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
ALE Low to Valid Data In
t
LLDV
2.5t
CLCL
- 5
t
MCS
+ 2t
CLCL
- 40
nS
t
MCS
= 0
t
MCS
>0
Port 0 Address to Valid Data In
t
AVDV1
3.0t
CLCL
- 20
2.0t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
ALE Low to
RD
or
WR
Low
t
LLWL
0.5t
CLCL
- 5
1.5t
CLCL
- 5
0.5t
CLCL
+ 5
1.5t
CLCL
+ 5
nS
t
MCS
= 0
t
MCS
>0
Port 0 Address to
RD
or
WR
Low
t
AVWL
t
CLCL
- 5
2.0t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
Port 2 Address to
RD
or
WR
Low
t
AVWL2
1.5t
CLCL
- 5
2.5t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
Data Valid to WR Transition
t
QVWX
-5
1.0t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
Data Hold after Write
t
WHQX
t
CLCL
- 5
2.0t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
RD
Low to Address Float
t
RLAZ
0.5t
CLCL
- 5
nS
RD
or WR high to ALE high
t
WHLH
0
1.0t
CLCL
- 5
10
1.0t
CLCL
+ 5
nS
t
MCS
= 0
t
MCS
>0
Note: t
MCS
is a time period related to the Stretch memory cycle selection. The following table shows the time period of t
MCS
for each selection of the Stretch value.