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參數(shù)資料
| 型號： | W79E648 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Fast 8051 Compatible microcontroller with a redesigned Processor |
| 中文描述： | 快速8051兼容微控制器重新設(shè)計的處理器 |
| 文件頁數(shù)： | 24/80頁 |
| 文件大小： | 407K |
| 代理商： | W79E648 |
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Preliminary W79E648
- 24 -
HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
Timed Access
Bit:
7
6
5
4
3
2
1
0
TA.7
TA.6
TA.5
TA.4
TA.3
TA.2
TA.1
TfA.0
Mnemonic: TA
Address: C7h
TA: The Timed Access register controls the access to protected bits. To access protected bits, the
user must first write AAH to the TA. This must be immediately followed by a write of 55H to TA.
Now a window is opened in the protected bits for three machine cycles, during which the user can
write to these bits.
Timer 2 Control
Bit:
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C T
/
2
CP RL
/
2
Mnemonic: T2CON
Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set when the count is
equal to the capture register in down count mode. It can be set only if RCLK and TCLK are
both 0. It is cleared only by software. Software can also set or clear this bit.
EXF2: Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2 overflow will
cause this flag to set based on the
CP RL
/
transition, this flag must be cleared by software. Setting this bit in software or detection of a
negative transition on T2EX pin will force a timer interrupt if enabled.
RCLK: Receive Clock Flag: This bit determines the serial port 0 time-base when receiving data in
serial modes 1 or 3. If it is 0, then timer 1 overflow is used for baud rate generation, otherwise
timer 2 overflow is used. Setting this bit forces timer 2 in baud rate generator mode.
TCLK: Transmit Clock Flag: This bit determines the serial port 0 time-base when transmitting data in
modes 1 and 3. If it is set to 0, the timer 1 overflow is used to generate the baud rate clock
otherwise timer 2 overflow is used. Setting this bit forces timer 2 in baud rate generator mode.
EXEN2: Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if
Timer 2 is not generating baud clocks for the serial port. If this bit is 0, then the T2EX pin will
be ignored, otherwise a negative transition detected on the T2EX pin will result in capture or
reload.
TR2:
Timer 2 Run Control. This bit enables/disables the operation of timer 2. Clearing this bit will
halt the timer 2 and preserve the current count in TH2, TL2.
Address: C8h
TF2:
2
, EXEN2 and DCEN bits. If set by a negative
C T
/
2
: Counter/Timer Select. This bit determines whether timer 2 will function as a timer or a counter.
Independent of this bit, the timer will run at 2 clocks per tick when used in baud rate generator
mode. If it is set to 0, then timer 2 operates as a timer at a speed depending on T2M bit
(CKCON.5), otherwise it will count negative edges on T2 pin.
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