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參數資料
型號: W79E648
廠商: WINBOND ELECTRONICS CORP
英文描述: Fast 8051 Compatible microcontroller with a redesigned Processor
中文描述: 快速8051兼容微控制器重新設計的處理器
文件頁數: 63/80頁
文件大小: 407K
代理商: W79E648
Preliminary W79E648
Publication Release Date: 05/31/2004
- 63 - Revision A1
16. SECURITY BITS
1. Using device programmer, the Flash EPROM can be programmed and verified repeatedly. Until
the code inside the Flash EPROM is confirmed OK, the code can be protected. The protection of
Flash EPROM and those operations on it are described below. The W79E648 has Special Setting
Register which can be accessed by device programmer. The register can only be accessed from
the Flash EPROM operation mode. Those bits of the Security Registers can not be changed once
they have been programmed from high to low. They can only be reset through erase-all operation.
If you needn’t have ISP function, please don’t fill “FF” code on LD memory. The writer always
writes AP and LD flashs every time.
Default 1 for each bit.
B0 : 0-> Data out lock
B1: 0 -> Movc Inhibited
B4: 0 -> Enable H/W reboot with P2.6, P2.7
B5: 0 -> Eable H/W reboot with P4.3
B0
B1
Option Bits
Security Bits
B2
B3
B4
B5
B6
B7
B7: 1: XT > 24M hz, 0: XT < 24M hz.
B0: Lock bit
This bit is used to protect the customer's program code in the W79E648. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
Flash EPROM data and Special Setting Registers can not be accessed again.
B1: MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
B4: H/W Reboot with P2.6 and P2.7
If this bit is set to logic 0, enable to reboot 4k LDFlash mode while RST =H, P2.6 = L and P2.7 = L
state. CPU will start from LDFlash to update the user’s program.
B5: H/W Reboot with P4.3
If this bit is set to logic 0, enable to reboot 4k LDFlash mode while RST =H and P4.3 = L state. CPU
will start from LDFlash to update the user’s program
B7: Select clock freqency.
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