
Preliminary W79E648
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Table 9. Time-out values for the Watchdog timer
WD1
WD0
Watchdog
Interval
2
17
2
20
2
23
2
26
Number of
Clocks
Time
@ 1.8432 MHz
Time
@ 10 MHz
Time
@ 25 MHz
0
0
131072
71.11 mS
13.11 mS
5.24 mS
0
1
1048576
568.89 mS
104.86 mS
41.94 mS
1
0
8388608
4551.11 mS
838.86 mS
335.54 mS
1
1
67108864
36408.88 mS
6710.89 mS
2684.35 mS
The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not
disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into
a known state.
The control bits that support the Watchdog timer are discussed below.
Watchdog Control
WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the
watchdog timer. If the Watchdog interrupt is enabled (EIE.4), then an interrupt will occur (if the
global interrupt enable is set and other interrupt requirements are met). Software or any reset
can clear this bit.
WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs.
This bit is useful for determined the cause of a reset. Software must read it, and clear it
manually. A Power-fail reset will clear this bit. If EWT = 0, then this bit will not be affected by
the watchdog timer.
EWT: WDCON.1 - Enable Watchdog timer Reset. This bit when set to 1 will enable the Watchdog
imer reset function. Setting this bit to 0 will disable the Watchdog timer reset function, but will
leave the timer running.
RWT: WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog timer and to
restart it. This bit is self-clearing, so after the software writes 1 to it the hardware will
automatically clear it. If the Watchdog timer reset is enabled, then the RWT has to be set by
the user within 512 clocks of the time-out. If this is not done then a Watchdog timer reset will
occur.