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參數資料
| 型號： | W9320 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ADPCM Codec(ADPCM編解碼器) |
| 中文描述： | A/MU-LAW, ADPCM CODEC |
| 文件頁數： | 13/35頁 |
| 文件大小： | 444K |
| 代理商： | W9320 |
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W9320
Publication Release Date: August 1997
- 13 -
Revision A1
controller. Two timing controls, a double 8-bit transfer mode and a single 16-bit transfer mode, are
available when SSP EN is held low to select the setup registers. The data rate for the SSP CLK
ranges from 0 to 2048 KHz. The data is shifted out of the SSP port on the falling edge of SSP CLK,
and shifted into the SSP port on the rising edge of the SSP CLK. This latch operation is the reverse of
the serial data port in the DSP engine.
The 16 byte registers are selected by bits 3 to 0 in the first byte from the SSP Rx pin as shown in
Figure 7-6 to 7-9. Bit 7 of the first byte indicates whether the status is read (logic 1) or write (logic 0).
The second byte is the data word (D7:D0). The description of setup and status registers, BR0--BR15
is described in greater detail in the next section 8. (Control and Status Registers).
SSP EN
SSP CLK
SSP Tx
SSP Rx
1
2
3
4
5
6
7
8
A3
A2
A1
A0
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
High Impedence
Don't Care
Don't Care
Don't Care
W
Figure 7-6 Double 8 bit for Write Operation of SSP Register
D7
D6
D5
D4
D3
D2
D1
D0
SSP EN
SSP CLK
SSP Tx
SSP Rx
1
2
3
4
5
6
7
8
A3
A2
A1
A0
1
2
3
4
5
6
7
8
Don't Care
Don't Care
R
Figure 7-7 Double 8 bit for Read Operation of SSP Register
SSP EN
SSP CLK
SSP Tx
SSP Rx
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
High Impedence
A3
A2
A1
A0
Don't Care
D7
D6
D5
D4
D3
D2
D1
D0
Don't Care
W
Figure 7-8 Single 16 bit for Write Operation of SSP Register
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