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參數資料
| 型號： | W9320 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ADPCM Codec(ADPCM編解碼器) |
| 中文描述： | A/MU-LAW, ADPCM CODEC |
| 文件頁數： | 31/35頁 |
| 文件大小： | 444K |
| 代理商： | W9320 |
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W9320
Publication Release Date: August 1997
- 31 -
Revision A1
TG
TI-
TI+
VAG
RO
AXO-
AXO+
VDSP
VEXT
PI
PO+
PDI/RESET
SSP En
VDD
FSR
BCLKR
DR
C1+
C1-
Vss
MCLK (SCP)
DT
BCLKT
FST
SSP Rx
SSP Tx
SSP CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
22
28
27
26
25
24
23
21
20
19
18
17
16
15
Battery Power
8 K Hz Frame Sync. Input
2048 KHz Data Rate
ADPCM Data Output
System Clock= 10.24/16.384 MHz
ADPCM Data Input
Micro-Controller
ADPCM Chip
150
10 K
10 K
20 K
3 K
R0 = 600
Tip
N = 0.5
N = 1
Ring
N.C.
N.C.
N.C.
N.C.
0.1 uF
0.1 uF
0.1 uF
Figure 10-2 Typical Transformer Application
11. HOW TO PROGRAM THE TONE GENERATOR
11.1 Introduction
The chip can enable the tone generator by setting BR7(b3) to logic "1". Under this operation, the
ADPCM decoder will be disabled. The tone generator is implemented by the DSP engine based on
the function "c" os(nx)
.
The procedure for programming the W9320 tone generator is as follows.
Setting BR7(b3) to logic "1" turns on the tone generator. In addition, BR7(b1:b0) must be set to logic
"0" to avoid turning on tone1 or tone2, without first programming the coefficients for freqency and
attenuation.
Setup the 12-bit coefficients for freqency and attenuation. First the 8 least significant bits(LSB) of 12-
bit coefficients must be written into BR4(b7:b0); then the 4 most significant bits(MSB) of 12-bit
coefficients and address parameter will be written into BR5(b3:b0) and BR5(b7:b6) simultaneously in
the same cycle. The cycle of setup coefficients is once every FSR cycle (125
μ
S) because the DSP
engine in device can access the SSP register only at every FSR cycle when the 12-bit coefficient in
written into SSP refister.
Poll BR7(b7) until BR7(b7) becomes a logic "0" before writing another 12-bit coefficent for BR4 and
BR5.
Set BR7(b1:b0) to logic "1" selects the tone 1 or tone2 generator.
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