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參數(shù)資料
| 型號： | W9320 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ADPCM Codec(ADPCM編解碼器) |
| 中文描述： | A/MU-LAW, ADPCM CODEC |
| 文件頁數(shù)： | 8/35頁 |
| 文件大小： | 444K |
| 代理商： | W9320 |
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W9320
- 8 -
6. BLOCK DIAGRAM
VEXT
C1+
VDD
C1-
VDSP
AXO+
AXO-
Analog
Smoothing
Filter
Analog
LPF
Digital
Σ
Demodulator
Digital
Anti-Alias
Intp. Filter
+
-
RO
+
-
PO+
-
+
PO-
PI
+
-
Vref
-
+
TI-
TI+
TG
Tx Gain
Control
Analog
Σ
Modulator
ADigital
Digital
HPF
Charge-Pump &
5 volt Regulator for
Analog Processing
3 volt Regulator for
Digital Signal Processor
2.5V
Reference Voltage
VAG
Power Supply
Management System
Codec-filter
Serial
Data
Port
(SDP)
ADPCM
Decoder
ADPCM
Encoder
NoiseBurst
Detection
Universal
Tone
Generator
Rx Atten.
Control
Sidetone
Gain
Digital
Rx Gain
Mu/A Law
Expander
or
Linear
Mu/A Law
Compressor
DSP Engine
DR
FSR
BCLKR
FST
BCLKT
DT
Serial Setup Port & 16 * 8 Bits
Setup and Status Registers
Sequence
and
Control
SSP EN
SSP CLK
SSP Tx
SSP Rx
MCLK
PDI/RESET
Figure 6-1 Winbond ADPCM
Σ
Codec Block Diagram
7. FUNCTIONAL DESCRIPTIONS
Figure 6-1 illustrates the functional blocks of the Winbond ADPCM
Σ
codec. The chip can be divided
into four subsystems which are described in the following subsections.
7.1. Power Supply Management System
In this block two groups comprise the power supply management system. One group is a 5-volt power
supply system for all analog signal processing. The second group is a 3-volt power supply system for
all digital signal processing.
7.1.1. Power Supply for All Analog Signals Processing
All analog circuits except for output power amplifiers AXO and PO are supplied with 5-volt power.
This voltage may be applied directly to the V
DD
pin or by the 5 volt charge pump circuit. Note that the
power drivers AXO and PO are powered by the V
EXT
pin which is the main positive power supply pin.
When V
EXT
= +5V
±
5% (e.g. base station applications) V
DD
is an input pin and should be connected
externally to the V
EXT
pin. The charge pump capacitor C1+ and C1- should not be used and the
BR0[b2] must be set as a logic "1" to disable the charge pump circuit. In this case V
EXT
and V
DD
can
share the same 0.1 uF decoupling capacitor to V
SS
.
When V
EXT
= 2.7 to 5.25 volts (e.g. battery applications) V
DD
is a 5 volt charge pump circuit output
and should not be connected to V
EXT
. V
DD
should be decoupled to Vss with a 0.1
μ
F capacitor. This
pin cannot be used for powering external loads.
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