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參數資料
| 型號： | W9320 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ADPCM Codec(ADPCM編解碼器) |
| 中文描述： | A/MU-LAW, ADPCM CODEC |
| 文件頁數： | 5/35頁 |
| 文件大小： | 444K |
| 代理商： | W9320 |
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W9320
Publication Release Date: August 1997
- 5 -
Revision A1
4.2. Analog Interface, continued
PIN NAME
PI
PIN NO.
10
I/O
I
FUNCTION
This pin is the inverting input to the PO- (pin-11) power amplifier. It
may be dc referenced to either the VAG pin or V
EXT
/2 by BR2 (b7).
This pin and PO- are used to set the gain by using external
resistors. Connecting this pin to V
DD
will power down the chip and
the PO+ and PO- outputs will be high impedance.
This pin is the inverting power amplifier output. Its operation is
same as the AXO- (pin-6). In the application, this pin can drive the
speaker on the receiver.
This pin is the non-inverting power amplifier output. Its operation is
the same as the AXO+ (pin-7). In the application, this pin can drive
the speaker of the receiver.
PO-
11
O
PO+
12
O
4.3. ADPCM/PCM Serial Interface
PIN NAME
MCLK
PIN NO.
21
I/O
I
FUNCTION
This pin is the system master clock input pin. It typically accepts
10.24 MHz or 16.384 MHz for Winbond cordless applications. This
pin is the oscillator input.
This pin is an 8 KHz pulse train for transmission of frame syncs.
This pin synchronizes the output of the DT pin (pin-20).
The bit clock for transmission. It shifts out the data on the DT pin
on the rising edge. The frequency may vary from 128K to 2048
KHz.
This pin is tri-state output data for transmission controlled by FST
and BCLKT pin.
This pin is an 8K Hz pulse train to receive frame syncs. This pin
synchronizes the input of the DR pin (pin-25).
This pin is the receive bit clock. It shifts data on the DR pin into the
chip on the falling edge. The frequency varies from 128K to 2048
KHz.
This pin is the receive input data controlled by the FSR and BCLKR
pins.
FST
18
I
BCLKT
19
I
DT
20
O
FSR
27
I
BCLKR
26
I
DR
25
I
4.4 Serial Setup Port(SSP) Interface
PIN NAME
SSP EN
PIN NO.
14
I/O
I
FUNCTION
This pin is the enable signal for SSP setup. This pin is held low to
select the16 control and status registers. There are two timing
controls. One is for double 8 bit transfer mode; the other control is
for the single 16 bit transfer mode. See the timing diagram, Figure
7-6 to 7-9, in Section 7.4.
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