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參數(shù)資料
| 型號(hào)： | W9320 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ADPCM Codec(ADPCM編解碼器) |
| 中文描述： | A/MU-LAW, ADPCM CODEC |
| 文件頁數(shù)： | 18/35頁 |
| 文件大小： | 444K |
| 代理商： | W9320 |
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W9320
- 18 -
8.2.3. Byte Register 2 (BR2)
This register controls the operations of the receive path in the
Σ
code-filter block. All bits are cleared
when the PDI/RESET pin is set to logic zero.
B7
B6
AXO
Enable
B5
PO
B4
B3
RO
Mute
B2
B1
B0
BR2
Reference
Point
Select
r/w
r/w
Disable
r/w
Reserved
r/w
Receive
Atten.[2]
r/w
Receive
Atten.[1]
r/w
Receive
Atten.[0]
r/w
Reference Point Select (b7):
This bit determines the reference voltage for power amplifiers such as RO, AXO, and PO. The output
of the VAG pin is the reference voltage. Setting this bit sets the reference voltage to 2.5 volts. When
this bit is cleared, the reference voltage is the default value of VEXT/2.
AXO Enable (b6):
This bit determines the status of the power amplifier AXO. Setting the bit will enable the operation of
the AXO amplifier. When this bit is cleared, the amplifier AXO will be disabled by default. In power
down mode, the output pins of AXO are high impedance.
PO Disable (b5):
This bit determines the status of power amplifier PO. Setting the bit will disable the operation of PO
amplifier. When this bit is cleared, the amplifier PO is enabled by default. In the power down mode,
the output pins of PO are high impedance.
Reserved (b4):
This bit is reserved.
RO Mute (b3):
Setting this bit will force the input of the RO amplifier to ground. The RO remains offset in order to
avoid audible " pops" when turning the block on and off.
Receive Attenuation[2:0] (b2:b0):
These three bits control the receive attenuation as shown in Table 8-5. The attenuation range can be
set from 0 to -7 dB in -1 dB steps.
RECEIVE ATTEN.[2]
(B2)
0
RECEIVE ATTEN.[1]
B1)
0
RECEIVE ATTEN.[0]
(B0)
0
RECEIVE
ATTENUATION (DB)
0
-1
-2
-3
0
0
0
0
1
1
1
0
1
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