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參數(shù)資料
| 型號： | W9320 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ADPCM Codec(ADPCM編解碼器) |
| 中文描述： | A/MU-LAW, ADPCM CODEC |
| 文件頁數(shù)： | 21/35頁 |
| 文件大小： | 444K |
| 代理商： | W9320 |
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W9320
Publication Release Date: August 1997
- 21 -
Revision A1
Ready for Writing BR4 and BR5 (b7):
This read-only bit indicates whether parameters have been written into the BR4 and BR5 register.
This bit is set after writing to BR5. This bit is cleared when the internal DSP Engine reads from the
BR4 and BR5 registers.
Noise Burst Detect Enable (b6):
This is a read-only/write-only bit. Setting this bit and bit 3 to 0 enables the noise burst detection
routine. If noise is detected, this bit is cleared and can be polled by an external micro-controller. This
mutes the receive path.
2/6 Delay (b5):
This bit controls the frame delay status. Setting this bit inserts a 6-frame delay between frame control
changes. Clearing this bit inserts a 2-frame delay between frame control changes.
Don't Care (b4):
No effect whenever the bit is read or written to by an external micro-controller.
Tone Generator Enable (b3):
Setting this bit performs the tone generator routine instead of the ADPCM decoder. In addition, the
noise burst detection will be disabled. The result of the tone generator will be passed to the ADPCM
encoder to compress the tone and transmit the encoded result to the DT pin.
Reserved (b2):
This bit is reserved.
Tone 1 Enable (b1):
Setting this bit enables the tone 1 routine for the tone generator. When this bit is cleared, the tone1
routine is disabled.
Tone 2 Enable (b0):
Setting this bit enables the tone 2 routine for the tone generator. When this bit is cleared, the tone 2
routine is disabled. If DTMF is enabled, the user must set tone 1 and tone 2 to enable.
8.2.9.
Byte Register 8 (BR8)
This register contains miscellaneous control bits. All bits are cleared when the PDI/RESET pin is set
to logic zero.
B7
B6
B5
B4
B3
B2
B1
B0
BR8
S/W
Encoder
Reset
r/w
S/W
Decoder
Reset
r/w
Linear
Codec
Mode
r/w
HPF
Disable
r/w
Reserved
Reserved
Reserved
Reserved
Software Encoder Reset (b7):
Setting this bit forces the device to execute the ADPCM encoder initialization every time the encoder
receives an interrupt.
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