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參數資料
| 型號： | W9320 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ADPCM Codec(ADPCM編解碼器) |
| 中文描述： | A/MU-LAW, ADPCM CODEC |
| 文件頁數： | 14/35頁 |
| 文件大小： | 444K |
| 代理商： | W9320 |
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W9320
- 14 -
SSP Rx
D7
D6
D5
D4
D3
D2
D1
D0
SSP EN
SSP CLK
SSP Tx
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Don't Care
A3
A2
A1
A0
Don't Care
R
Figure 7-9 Single 16 bit for Read Operation of SSP Register
7.5. Sequence and Control
This block generates some internal clocks, providing clocks such as 1.024 MHz and 8 KHz for
Σ
codec-filter operation. The master clock MCLK, which supports the clock of the DSP engine, may be
asynchronous to all other blocks. Its frequency is typically 10.24 MHz or 16.384 MHz for cordless
applications using Winbond chips.
The
Σ
codec-filter may use the BCLKR pin as a direct 1.024MHz input. The rising edge of this input
clock must be approximately aligned with the rising edge of the FST. This mode requires that the
ADPCM transmit and receive be controlled by the BCLKT pin. This is configured by the SSP port
through the BR0(b7) register.
There are two ways of forcing the device into a low power consumption condition in power down
mode. One way is the hardware power down mode where the PDI/RESET pin is held to logic 0. The
other way is the software power down mode where the register BR0(b1:b0) is set through the SSP.
When the BR0(b1) setting initiates an analog power down, all clocks for analog signal processing will
be halted. To initiate a digital power down, the BR0(b0) register can be programmed to logic 1 to halt
all clocks for all digital signal processing. When the chip is powered down, the VAG, TG, RO, PO,
AXO, DT and SSP Tx outputs are all high impedance. When the power is reactivated from the power
down mode, the ADPCM algorithm is reset to the CCITT initiate state.
7.6. I/O Level
Digital I/O for the device can be programmed in either Mu-law or A-law. Full scale and zero words for
these two log-PCM forms are shown in Table 7-1. For analog signal processing, the maximum
transmit level is 3.17 dBm0 for Mu-Law or 3.14 dBm0 for A-Law. These values meet the CCITT
G.711specifications.
MU-LAW
Segment Bits
000
111
111
000
A-LAW
Level
Sign
1
1
0
0
Step Bits
0000
1111
1111
0000
Sign
1
1
0
0
Segment Bits
010
101
101
010
Step Bits
1010
0101
0101
1010
+ max. scale
+Zero
- Zero
- max. scale
Table 7-1 Full Scale and Zero Word for Mu/A-Law
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