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參數資料
| 型號： | W9320 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ADPCM Codec(ADPCM編解碼器) |
| 中文描述： | A/MU-LAW, ADPCM CODEC |
| 文件頁數： | 16/35頁 |
| 文件大小： | 444K |
| 代理商： | W9320 |
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W9320
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Mode Select[1:0] (b4:b3):
The function modes are shown in Table 8-2. The ADPCM Codec mode performs a combination of
PCM codec and ADPCM transcoder in full duplex. The PCM codec mode is a subset of the ADPCM
codec mode, where only the PCM codec is executed. The CCITT test mode uses the CCITT ADPCM
test vectors to do conformance testing. Enabling this mode will remove the
Σ
codec-filter operation.
The test vectors go through the SSP port in BR9[b7:b0] and BR10[b7:b0]. See the BR9 and BR10
descriptions for more details. The battery test mode allows testing of the voltage present at the V
EXT
pin. In this mode, the HPF output in register BR8[b4] must be disabled. Note that the steady linear
code for the V
EXT
pin will be delayed by about 60 samples. The output result of linear 14 bits is stored
in registers BR9 and BR10.
FUNCTION MODE SELECT[1:0] (B4:B3)
TYPE
00
ADPCM Codec
01
PCM Codec
10
CCITT Test
11
Battery Test
Table 8-2 Function Mode Selection
Charge Pump Disable (b2):
Setting this bit disables the 5 volt charge pump. In this mode, the charge pump capacitor C1+ and
C1- should not be used and the V
DD
pin should be connected externally to the V
EXT
pin.
Analog Power Down (b1):
Setting this bit causes an analog power down. In this mode, all clocks for analog processing (e.g. the
Σ
codec) will be halted to reduce power consumption. The analog circuit will not operate normally
until this bit is cleared.
Digital Power Down (b0):
Setting this bit causes a digital power down. In this mode, all clocks for digital processing (e.g. the
DSP engine) will be halted to reduce power consumption. The digital circuit and the ADPCM
initialization will not operate until this bit is cleared.
8.2.2. Byte Register 1 (BR1)
This register controls the sidetone gain value and transmit gain. This register can also mute the
transmit signal. All bits are cleared when the PDI/RESET pin is set to logic zero.
B7
B6
B5
B4
B3
B2
B1
B0
BR1
Reserved
Sidetone
Gain[2]
r/w
Sidetone
Gain[1]
r/w
Sidetone
Gain[0]
r/w
Transmit
Mute
r/w
Transmit
Gain[2]
r/w
Transmit
Gain[1]
r/w
Transmit
Gain[0]
r/w
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