
Data Sheet
W66910 PCI ISDN S/T-Controller
Publication Release Date:
Feb,2001
Revision 1.0
-12 -
data rate can be multiplexed on this signal. Needs external pull-up.
ISDN Signals and External Crystal
I
S/T bus receiver input (negative).
I
S/T bus receiver input (positive).
O
S/T bus transmitter output (positive).
O
S/T bus transmitter output (negative).
I
Crystal or Oscillator clock input. The clock frequency:
7.68MHz
±
100PPM.
O
Crystal clock output. Left unconnected when using oscillator.
Functional Test
I
Used to enable normal operation (1) or enter test mode (0).
Peripheral Control
O
Timer 2 output. A square wave with 50 % duty cycle, 1~63 ms period
can be generated.
I
A level change (either direction) will generate a maskable interrupt on
the interrupt request pin INT#.
I
A level change (either direction) will generate a maskable interrupt on
the interrupt request pin INT#.
I/O
When confiured as simple IO mode (PCTL:XMODE = 0), these pins can
read/write data from/to peripheral components. The pin directions are
selected via register. After hardware reset, the output drivers are
disabled.
I/O
When configured as microprocessor mode (PCTL:XMODE = 1),
address and data are multiplexed on these pins.
O
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the Address Latch Enable output.
O
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the read pulse.
O
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the write pulse.
Power and Ground
I
Digital Power Supply (5V
±
5%).
I
Analog Power Supply (5V
±
5%).
I
Power Supply (5V
±
5%).
I
Digital Ground.
I
Analog Ground.
I
Ground.
SR1
SR2
SX1
SX2
XTAL1
49
50
54
55
56
XTAL2
57
TESTP
61
TOUT2
20
XINTIN0
52
XINTIN1
53
IO10-IO0
79,78,77,29,28,
27,26,4,3,2,1
XAD7-XAD0
29,28,27,26,
4,3,2,1
77
XALE
XRDB
78
XWRB
79
VDDD
VDDA
VDDB
VSSD
VSSA
VSSB
17,58,67,83
51
6,32,43,89
16,59,68,82
48
5,31,42,88