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參數(shù)資料
型號: W66910CD
廠商: WINBOND ELECTRONICS CORP
元件分類: 通信及網(wǎng)絡
英文描述: TE Mode ISDN S/T-Controller with Microprocessor Interface
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, QFP-100
文件頁數(shù): 59/81頁
文件大小: 681K
代理商: W66910CD
Data Sheet
W66910 PCI ISDN S/T-Controller
Publication Release Date:
Feb,2001
Revision 1.0
-59 -
MAC1 Monitor Transmit Channel 1 Active (Read Only)
Data transmission is in progress in GCI mode Monitor channel 1.
0: the previous transmission has been terminated. Before starting a transmission, the microprocessor should verify
hat the transmitter is inactive.
1: after having written data into the Monitor Transmit Channel 1 (MO1X) register, the microprocessor sets this bit to 1.
This enables the MX bit to go active (0), indicating the presence of valid Monitor channel data (contents of MOX) in
he correspond frame.
GACT GCI Switching Active
Determines which CODEC interface is to be activated in B channle switching. Valid only in GCI master mode. In GCI slave
mode, PCM ports are always enabled.
0: PCM port is used.
1: GCI bus is used.
TLP Test Loop
When this bit is set to 1 both the DU and DD lines are internally connected together. External input on DD is ignored. Valid in
GCI slave mode.
GRLP GCI Mode Remote Loop-back
Setting this bit to 1 activates the remote loop-back function. The 2B+D channels data received from the GCI bus (DD) interface
are looped to the transmitted channels (DU). Valid in GCI slave mode.
SPU Software Power Up
PD Power Down
SPU
PD
0
1
After U transceiver power down, W66910 will receive the indication DC (Deactivation Confirmation) from
GCI bus and then software has to set SPU
0, PD
1 to acknowledge U transceiver, by pulling DU pin to
HIGH. W66910 remains normal operation.
1
0
Setting SPU
1, PD
0 will pull the GCI bus DU line to low. This will enforce connected layer 1 devices
(U transceiver) to deliver GCI bus clocking.
0
0
After reception of the indication PU (Power Up indication) the reaction of the microprocessor should be:
To write an AR (Activate Request command) as C/I command code in the CIX register.
To reset the SPU bit and wait for the following ICC (indication code change) interrupt.
1
1
Unused.
GMODE GCI Mode
0: Layer 1 is S/T interface; GCI is in master mode. This is default setting.
1: Layer 1 is U interface; GCI is in slave mode.
Description
8.1.33 Peripheral Data Register 1
Value after reset: Undefined
XDATA1
Read/Write
Address 3DH
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