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參數(shù)資料
型號(hào): W66910CD
廠商: WINBOND ELECTRONICS CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: TE Mode ISDN S/T-Controller with Microprocessor Interface
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, QFP-100
文件頁(yè)數(shù): 76/81頁(yè)
文件大小: 681K
代理商: W66910CD
Data Sheet
W66910 PCI ISDN S/T-Controller
Publication Release Date:
Feb,2001
Revision 1.0
-76 -
Parameter
ta1
ta2
ta3
Parameter Descriptions
PBCK pulse high
PBCK pulse low
Frame clock asserted from
PBCK
PTXD data delay from PBCK
Frame clock deasserted from
PBCK
PTXD hold time from PBCK
PRXD setup time to PBCK
PRXD hold time from PBCK
Min.
195
Nominal
325
325
Max.
455
20
Remarks
Unit = ns
ta4
ta5
20
20
ta6
ta7
ta8
Note
: The PCM clocks are locked to the S/T receive clock. At every two or three PCM frame time (125
μ
s), PBCK and PFCK1,
PFCK2 may be adjusted by one local oscillator cycle (130 ns) in order to synchronize with S/T clock. This shift is made on the
LOW level time of PBCK and the HIGH level time is not affected. This introduces jitters on the PBCK, PFCK1 and PFCK2 with
jitter amplitude 260 ns (peak-to-peak) and jitter frequency about 2.67~4 kHz.
10
20
10
9.4.2 8-bit Microprocessor Timing
Intel mode read cycle timing
RD#
t1
ALE
t3
t11
t5
t10
AD<7:0>
CS#
t8
t2
A<7:0>
D<7:0>
A<7:0>
t4
t9
t6
t7
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相關(guān)代理商/技術(shù)參數(shù)
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