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參數資料
| 型號： | W66910CD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | TE Mode ISDN S/T-Controller with Microprocessor Interface |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, QFP-100 |
| 文件頁數： | 67/81頁 |
| 文件大小： | 681K |
| 代理商： | W66910CD |
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Data Sheet
W66910 PCI ISDN S/T-Controller
Publication Release Date:
Feb,2001
Revision 1.0
-67 -
XME Transmit Message End
n transparent mode, setting this bit indicates the end of the whole frame transmission. The B1_ch HDLC controller transmits the
data in FIFO and automatically appends the CRC and the closing flag sequence in transparent mode.
n extended transparent mode, setting this bit stops the B1_XFIFO data transmission.
This bit is write-only. It's auto-clear.
XRST Transmitter Reset
Setting this bit resets the B1_ch HDLC transmitter and clears the B1_XFIFO. The transmitter will send inter frame time fill
pattern on B channel in transparent mode, or idle pattern in extended transparent mode. This command also results in a transmit
FIFO ready condition.
This bit is write only. It's auto-clear.
8.2.4 B1_ch Mode Register B1_MODE
Value after reset: 00H
7
6
MMS
ITF
EPCM B1_SW1 B1_SW0 SW56
MMS Message Mode Setting
Determines the message transfer modes of the B1_ch HDLC controller:
0: Transparent mode. In receive direction, address comparison is performed on each frame. The frames with matched address are
stored in B1_RFIFO. Flag deletion, CRC check and zero bit deletion are performed. In transmit direction, the data is transmitted
with flag insertion, zero bit insertion and CRC generation.
1: Extended transparent mode. In receive direction, all data are received and stored in the B1_RFIFO. In transmit direction, all
data in the B1_XFIFO are transmitted without alteration.
ITF Inter-frame Time Fill
Defines the inter-frame time fill pattern in transparent mode.
0 : Mark. The binary value "1" is transmitted.
1 : Flag. This is a sequence of "01111110".
EPCM Enable PCM Transmit/Receive
0 : Disable data transmit/ receive to/from PCM port. The frame synchronization clock PFCK1 is held LOW.
1 : Enable data transmit/ receive to/from PCM port. The frame synchronization clock PFCK1 is active.
B1_SW1-0 B Channel Switching Select
These two bits, along with PXC bit in PCTL register, determine the connection in B1 channel. See section 7.4 for details.
Note
: The connection with microprocessor is through HDLC controller. When HDLC connects with layer 1, either transparent or
extended transparent mode can be used. When HDLC connects with PCM port/GCI bus, only extended transparent mode can be
used and the EPCM bit must be set to enable PCM function.
SW56 Switch 56 Traffic
Read/Write
Address 23H
5
4
3
2
1
0
FTS1
FTS0
相關PDF資料 |
PDF描述 |
|---|---|
| W6691 | ISDN S/T Interface Transceiver |
| W6691CD | ISDN S/T Interface Transceiver |
| W6691CP | ISDN S/T Interface Transceiver |
| W6692 | PCI Bus ISDN S/T Interface Controller(PCI總線的ISDN S/T接口控制器) |
| W6693A | USB Bus ISDN S/T Interface Controller(USB總線的ISDN S/T接口控制器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W6691CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ISDN S/T Interface Transceiver |
| W6691CP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ISDN S/T Interface Transceiver |
| W6692 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:PCI Bus ISDN S/T-Controller |
| W6692A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
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